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Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor
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International Symposium on Computer Architecture archive
Proceedings of the 36th annual international symposium on Computer architecture table of contents
Austin, TX, USA
SESSION: Speculative threading and parallelization table of contents
Pages 484-495  
Year of Publication: 2009
ISBN:978-1-60558-526-0
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Authors
Shailender Chaudhry  Sun Microsystems, Inc., Santa Clara, CA, USA
Robert Cypher  Sun Microsystems, Inc., Santa Clara, CA, USA
Magnus Ekman  Sun Microsystems, Inc., Santa Clara, CA, USA
Martin Karlsson  Sun Microsystems, Inc., Santa Clara, CA, USA
Anders Landin  Sun Microsystems, Inc., Santa Clara, CA, USA
Sherman Yip  Sun Microsystems, Inc., Santa Clara, CA, USA
Håkan Zeffer  Sun Microsystems, Inc., Santa Clara, CA, USA
Marc Tremblay  Sun Microsystems, Inc., Santa Clara, CA, USA
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper presents Simultaneous Speculative Threading (SST), which is a technique for creating high-performance area- and power-efficient cores for chip multiprocessors. SST hardware dynamically extracts two threads of execution from a single sequential program (one consisting of a load miss and its dependents, and the other consisting of the instructions that are independent of the load miss) and executes them in parallel. SST uses an efficient checkpointing mechanism to eliminate the need for complex and power-inefficient structures such as register renaming logic, reorder buffers, memory disambiguation buffers, and large issue windows. Simulations of certain SST implementations show 18% better per-thread performance on commercial benchmarks than larger and higher-powered out-of-order cores. Sun Microsystems' ROCK processor, which is the first processor to use SST cores, has been implemented and is scheduled to be commercially available in 2009.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Tremblay, M., and Chaudhry, S. A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC Processor. In Proceedings of the 2008 International Solid-State Circuits Conference (Feb. 2008), pp. 82--83.
 
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Collaborative Colleagues:
Shailender Chaudhry: colleagues
Robert Cypher: colleagues
Magnus Ekman: colleagues
Martin Karlsson: colleagues
Anders Landin: colleagues
Sherman Yip: colleagues
Håkan Zeffer: colleagues
Marc Tremblay: colleagues