ACM Home Page
Please provide us with feedback. Feedback
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
Full text PdfPdf (667 KB)
Source
International Symposium on Computer Architecture archive
Proceedings of the 36th annual international symposium on Computer architecture table of contents
Austin, TX, USA
SESSION: Speculative threading and parallelization table of contents
Pages 474-483  
Year of Publication: 2009
ISBN:978-1-60558-526-0
Also published in ...
Authors
Carlos Madriles  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Pedro López  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Josep M. Codina  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Enric Gibert  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Fernando Latorre  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Alejandro Martinez  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Raúl Martinez  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Antonio Gonzalez  Intel Barcelona Research Center, Intel Labs - Universitat Politecnica de Catalunya, Barcelona, Spain
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 146,   Downloads (12 Months): 377,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1555754.1555813
What is a DOI?

ABSTRACT

Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with limited TLP impose important constraints to the global performance, as explained by Amdahl's law.

In this paper we propose a novel approach for leveraging multiple cores to improve single-thread performance in a multi-core design. The proposed technique features a set of novel hardware mechanisms that support the execution of threads generated at compile time. These threads result from a fine-grain speculative decomposition of the original application and they are executed under a modified multi-core system that includes: (1) mechanisms to support multiple versions; (2) mechanisms to detect violations among threads; (3) mechanisms to reconstruct the original sequential order; and (4) mechanisms to checkpoint the architectural state and recovery to handle misspeculations.

The proposed scheme outperforms previous hardware-only schemes to implement the idea of combining cores for executing single-thread applications in a multi-core design by more than 10% on average on Spec2006 for all configurations. Moreover, single-thread performance is improved by 41% on average when the proposed scheme is used on a Tiny Core, and up to 2.6x for some selected applications.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
2
3
 
4
5
 
6
J. D. Collins and D. M. Tullsen, Clustered Multithreaded Architectures - Pursuing Both Ipc and Cycle Time, in Int. Parallel and Distributed Processing Symp., April 2004
7
8
 
9
10
11
12
 
13
14
 
15
B. Kernighan, and S. Lin, An Efficient Heuristic Procedure for Partitioning of Electrical Circuits, in Bell System Technical Journal, 1970
16
17
 
18
 
19
 
20
A. Mendelson, J, Mandelblat, S. Gochman, A. Shemer, R. Chabukswar, E. Niemeyer, A. Kumar, "CMP Implementation in Systems Based on the Intel® CoreTM Duo Processor", in Intel Technology Journal, Volume 10, Issue 2, 2006
 
21
22
 
23
S. Thoziyoor, N. Muralimanohar, J. Ahn, and N. P. Jouppi, CACTI 5.1, Technical Report HPL-2008-20, HP Labs.
 
24
25
 
26
 
27

Collaborative Colleagues:
Carlos Madriles: colleagues
Pedro López: colleagues
Josep M. Codina: colleagues
Enric Gibert: colleagues
Fernando Latorre: colleagues
Alejandro Martinez: colleagues
Raúl Martinez: colleagues
Antonio Gonzalez: colleagues