Achieving predictable performance through better memory controller placement in many-core CMPs

ABSTRACT

In the near term, Moore's law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents the integration of a large number of memory controllers on-chip. With many cores, and few memory controllers, where to locate the memory controllers in the on-chip interconnection fabric becomes an important and as yet unexplored question. In this paper we show how the location of the memory controllers can reduce contention (hot spots) in the on-chip fabric and lower the variance in reference latency. This in turn provides predictable performance for memory-intensive applications regardless of the processing core on which a thread is scheduled. We explore the design space of on-chip fabrics to find optimal memory controller placement relative to different topologies (i.e. mesh and torus), routing algorithms, and workloads.

REFERENCES

• 1: H. Cain, K. Lepak, B. Schwarz, and M. H. Lipasti. Precise and accurate processor simulation. In Workshop On Computer Architecture Evaluation using Commercial Workloads, 2002.
• 2: Pat Conway , Bill Hughes, The AMD Opteron Northbridge Architecture, IEEE Micro, v.27 n.2, p.10-21, March 2007 [doi>10.1109/MM.2007.43]
• 3: Vinodh Cuppu , Bruce Jacob , Brian Davis , Trevor Mudge, A performance comparison of contemporary DRAM architectures, Proceedings of the 26th annual international symposium on Computer architecture, p.222-233, May 01-04, 1999, Atlanta, Georgia, United States
• 4: W. J. Dally, Virtual-Channel Flow Control, IEEE Transactions on Parallel and Distributed Systems, v.3 n.2, p.194-205, March 1992 [doi>10.1109/71.127260]
• 5: William Dally , Brian Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2003
• 6: Natalie Enright Jerger , Dana Vantrease , Mikko Lipasti, An Evaluation of Server Consolidation Workloads for Multi-Core Designs, Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization, p.47-56, September 27-29, 2007 [doi>10.1109/IISWC.2007.4362180]
• 7: Emanuel Falkenauer, Genetic Algorithms and Grouping Problems, John Wiley & Sons, Inc., New York, NY, 1998
• 8: Brinda Ganesh , Aamer Jaleel , David Wang , Bruce Jacob, Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling, Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, p.109-120, February 10-14, 2007 [doi>10.1109/HPCA.2007.346190]
• 9: Mark Horowitz , Chih-Kong Ken Yang , Stefanos Sidiropoulos, High-Speed Electrical Signaling: Overview and Limitations, IEEE Micro, v.18 n.1, p.12-24, January 1998 [doi>10.1109/40.653013]
• 10: Jingcao Hu , Radu Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, Proceedings of the 2003 Asia and South Pacific Design Automation Conference, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119818]
• 11: W. Hung , C. Addo-Quaye , T. Theocharides , Y. Xie , N. Vijaykrishnan , M. J. Irwin, Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture, Proceedings of the IEEE International Conference on Computer Design, p.430-437, October 11-13, 2004
• 12: Intel Tera-scale Computing Research Program: Teraflop Research Chip. http://techresearch.intel.com/articles/tera-scale/1449.htm.
• 13: John Kim , James Balfour , William Dally, Flattened Butterfly Topology for On-Chip Networks, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, p.172-182, December 01-05, 2007 [doi>10.1109/MICRO.2007.15]
• 14: Jae W. Lee , Man Cheuk Ng , Krste Asanovic, Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks, Proceedings of the 35th International Symposium on Computer Architecture, p.89-100, June 21-25, 2008
• 15: Kevin M. Lepak , Harold W. Cain , Mikko H. Lipasti, Redeeming IPC as a Performance Metric for Multithreaded Programs, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.232, September 27-October 01, 2003
• 16: Onur Mutlu , Thomas Moscibroda, Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, p.146-160, December 01-05, 2007 [doi>10.1109/MICRO.2007.40]
• 17: Onur Mutlu , Thomas Moscibroda, Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, Proceedings of the 35th International Symposium on Computer Architecture, p.63-74, June 21-25, 2008
• 18: Kyle J. Nesbit , Nidhi Aggarwal , James Laudon , James E. Smith, Fair Queuing Memory Systems, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.208-222, December 09-13, 2006 [doi>10.1109/MICRO.2006.24]
• 19: Daeho Seo , Akif Ali , Won-Taek Lim , Nauman Rafique , Mithuna Thottethodi, Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks, Proceedings of the 32nd annual international symposium on Computer Architecture, p.432-443, June 04-08, 2005
• 20: SPEC. SPEC benchmarks. http://www.spec.org.
• 21: Krishnan Srinivasan , Karam S. Chatha, A technique for low energy mapping and routing in network-on-chip architectures, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA [doi>10.1145/1077603.1077695]
• 22: Tilera Corporation. http://www.tilera.com.
• 23: Brian Towles , William J. Dally, Worst-case traffic for oblivious routing functions, Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures, August 10-13, 2002, Winnipeg, Manitoba, Canada [doi>10.1145/564870.564872]
• 24: TPC. TPC benchmarks. http://www.tpc.org.
• 25: S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pages 98--589, Feb. 2007.
• 26: David Wentzlaff , Patrick Griffin , Henry Hoffmann , Liewei Bao , Bruce Edwards , Carl Ramey , Matthew Mattina , Chyi-Chang Miao , John F. Brown III , Anant Agarwal, On-Chip Interconnection Architecture of the Tile Processor, IEEE Micro, v.27 n.5, p.15-31, September 2007 [doi>10.1109/MM.2007.89]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.2 Input/Output Devices
          Subjects: Channels and controllers

General Terms:
Design, Performance

Keywords:
chip multiprocessors, interconnection networks, memory controllers, routing algorithms