Hardware support for WCET analysis of hard real-time multicore systems

ABSTRACT

The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent a good design solution for such systems due to their high performance, low cost and power consumption characteristics. However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when accessing shared hardware resources. In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time analizability for the hard real-time tasks so that they can meet their deadlines. Moreover our architecture proposal provides high-performance for the non hard real-time tasks.

REFERENCES

• 1: MERASA EU-FP7 Project: www.merasa.org, 2007. RapiTime: Worst-case execution time analysis. User Guide.
• 2: Rapita Systems. Ltd., 2007.
• 3: Benny Akesson , Kees Goossens , Markus Ringhofer, Predator: a predictable SDRAM memory controller, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria [doi>10.1145/1289816.1289877]
• 4: Alexandru Andrei , Petru Eles , Zebo Peng , Jakob Rosen, Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip, Proceedings of the 21st International Conference on VLSI Design, p.103-110, January 04-08, 2008 [doi>10.1109/VLSI.2008.33]
• 5: Guillem Bernat , Antoine Colin , Stefan M. Petters, WCET Analysis of Probabilistic Hard Real-Time Systems, Proceedings of the 23rd IEEE Real-Time Systems Symposium, p.279, December 03-05, 2002
• 6: Bach D. Bui , Marco Caccamo , Lui Sha , Joseph Martinez, Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems, Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, p.101-110, August 25-27, 2008 [doi>10.1109/RTCSA.2008.42]
• 7: D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dynamic cache partitioning via columnization. In DAC, Los Angeles, CA, USA, 2000.
• 8: K. De Bosschere, W. Luk, X. Martorell, N. Navarro, M. O'boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat,
• 9: A. Seznec, P. Stenstrom, and O. Temam. High-performance embedded architecture and compilation roadmap. 2007. A. El-Haj-Mahmoud, A. S. AL-Zawawi, A. Anantaraman, and E. Rotenberg. Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. In CASES, San Francisco, CA, USA, 2005.
• 10: Ali El-Haj-Mahmoud , Eric Rotenberg, Safely exploiting multithreaded processors to tolerate memory latency in real-time systems, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA [doi>10.1145/1023833.1023837]
• 11: Infineon. Tricore 1. 32-bit Unified Processor Core v1.3, 2005.
• 12: I. A. Khatib, F. Poletti, D. Bertozzi, L. Benini, M. Bechara, H. Khalifeh, A. Jantsch, and R. Nabiev. A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. In DAC, San Francisco, CA, 2006.
• 13: Thomas Lundqvist , Per Stenström, Timing Anomalies in Dynamically Scheduled Microprocessors, Proceedings of the 20th IEEE Real-Time Systems Symposium, p.12, December 01-03, 1999
• 14: Rodolfo Pellizzoni , Marco Caccamo, Toward the Predictable Integration of Real-Time COTS Based Systems, Proceedings of the 28th IEEE International Real-Time Systems Symposium, p.73-82, December 03-06, 2007 [doi>10.1109/RTSS.2007.51]
• 15: J. Poovey. Characterization of the EEMBC Benchmark Suite. North Carolina State University, 2007.
• 16: I. Puaut and C. Pais. Scratchpad memories vs locked caches in hard real-time systems: a qualitative and quantitative comparison. Technical report, IRISA, Paris, France, 2006.
• 17: Jakob Rosen , Alexandru Andrei , Petru Eles , Zebo Peng, Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip, Proceedings of the 28th IEEE International Real-Time Systems Symposium, p.49-60, December 03-06, 2007 [doi>10.1109/RTSS.2007.13]
• 18: Tasking. Tricore v2.2 C Compiler, Assembler, Linker Reference Manual, 2005.
• 19: L. Thiele and R. Wilhelm. Design for time-predictability. In Design of Systems with Predictable Behaviour, 2004.
• 20: S. Uhrig, S. Maier, and T. Ungerer. Toward a processor core for real-time capable autonomic systems. In Proc. ISSPIT, Athens, Greece, 2005.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles

General Terms:
Design, Experimentation

Keywords:
analyzability, cache partitioning, hard real-time, interconnection network, multicore, real-time embedded systems, wcet