Dynamic MIPS rate stabilization in out-of-order processors

ABSTRACT

Today's microprocessor cores reach high performance levels not only by their high clock rate but also by the concurrent execution of a large number of instructions. Because of the relationship between power and frequency, it becomes attractive to run an OoO (Out-of-Order) core at a frequency lower than its nominal frequency in the context of embedded or real-time systems. Unfortunately, whereas OoO pipelines have high average throughput, their highly variable and hard-to-predict execution rate makes them unsuitable for real-time systems with hard or even soft deadlines. In this paper, we demonstrate that the execution time of an OoO processor can be stable and predictable by controlling its MIPS (Mega Instructions Per Second) rate via a PID (Proportional, Integral, and Differential gain) feedback controller and DVFS (Dynamic Voltage and Frequency Scaling). The stabilized processor uses much less power per committed instruction, because of the reduced average frequency. The EPI (Energy Per Instruction) is also cut by an average of 28% across our benchmark programs. Since a stable MIPS rate is maintained consistently with lower power/energy per instruction, OoO processors stabilized by a feedback controller can realistically be deployed in real-time systems. To demonstrate this capability we select a subset of the MiBench benchmarks that displays the widest execution rate variations and stabilize their MIPS rate in the context of a 1GHz Pentium III-like microarchitecture.

REFERENCES

• 1: Hakan Aydin , Vinay Devadas , Dakai Zhu, System-Level Energy Management for Periodic Real-Time Tasks, Proceedings of the 27th IEEE International Real-Time Systems Symposium, p.313-322, December 05-08, 2006 [doi>10.1109/RTSS.2006.48]
• 2: Luca Benini , Alessandro Bogliolo , Giovanni De Micheli, A survey of design techniques for system-level dynamic power management, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
• 3: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 4: Doug Burger and Todd M. Austin. The SimpleScalar Tool Set Version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin--Madison, May 1997.
• 5: Buce R. Childers, H. Tang and Rami Melhem, Adapting Processor Supply Voltage to Instruction-Level Parallelism, Koolchips 2000, during the 33rd Int'l. Symp. on Microarchitecture (MICRO--33), Monterey, CA, December 10, 2000.
• 6: Francisco J. Cazorla , Peter M. W. Knijnenburg , Rizos Sakellariou , Enrique Fernández , Alex Ramirez , Mateo Valero, Architectural support for real-time task scheduling in SMT processors, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA [doi>10.1145/1086297.1086320]
• 7: Francisco J. Cazorla , Peter M.W. Knijnenburg , Rizos Sakellariou , Enrique Fernández , Alex Ramirez , Mateo Valero, Predictable performance in SMT processors, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy [doi>10.1145/977091.977152]
• 8: L. T. Clark, Circuit Design of XScale Microprocessors, In Proceedings of the 2001 Symposium on VLSI Circuits, June, 2001.
• 9: Gilberto Contreras , Margaret Martonosi , Jinzhang Peng , Guei-Yuan Lueh , Roy Ju, The XTREM power and performance simulator for the Intel XScale core: Design and experiences, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.1, February 2007 [doi>10.1145/1210268.1210272]
• 10: Steven Dropsho , Greg Semeraro , David H. Albonesi , Grigorios Magklis , Michael L. Scott, Dynamically Trading Frequency for Complexity in a GALS Microprocessor, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.157-168, December 04-08, 2004, Portland, Oregon [doi>10.1109/MICRO.2004.18]
• 11: Krisztián Flautner , Steve Reinhardt , Trevor Mudge, Automatic performance setting for dynamic voltage scaling, Proceedings of the 7th annual international conference on Mobile computing and networking, p.260-271, July 2001, Rome, Italy [doi>10.1145/381677.381702]
• 12: Gene F. Franklin, Feedback Control of Dynamic Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1993
• 13: Stefan Valentin Gheorghita , Sander Stuijk , Twan Basten , Henk Corporaal, Automatic scenario detection for improved WCET estimation, Proceedings of the 42nd annual Design Automation Conference, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065610]
• 14: M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, p.3-14, December 02-02, 2001 [doi>10.1109/WWC.2001.15]
• 15: Greg Hamerly, Erez Perelman, Jeremy Lau, and Brad Calder, SimPoint 3.0: Faster and More Flexible Program Analysis, Journal of Instruction Level Parallelism, September 2005.
• 16: Juan Hamers , Lieven Eeckhout, Resource prediction for media stream decoding, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 17: A. Hergenhan , W. Rosenstiel, Static timing analysis of embedded software on advanced processor architectures, Proceedings of the conference on Design, automation and test in Europe, p.552-559, March 27-30, 2000, Paris, France [doi>10.1145/343647.343846]
• 18: Christopher J. Hughes , Praful Kaul , Sarita V. Adve , Rohit Jain , Chanik Park , Jayanth Srinivasan, Variability in the execution of multimedia applications and implications for architecture, Proceedings of the 28th annual international symposium on Computer architecture, p.254-265, June 30-July 04, 2001, Göteborg, Sweden
• 19: Christopher J. Hughes , Jayanth Srinivasan , Sarita V. Adve, Saving energy with architectural and frequency adaptations for multimedia applications, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 20: Yoshifumi Ikenaga, Employ Supply Voltage Control to Save Energy, Energy-saving Designs, NEC corporation.
• 21: Tohru Ishihara , Hiroto Yasuura, Voltage scheduling problem for dynamically variable voltage processors, Proceedings of the 1998 international symposium on Low power electronics and design, p.197-202, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280894]
• 22: Anoop Iyer , Diana Marculescu, Power and performance evaluation of globally asynchronous locally synchronous processors, Proceedings of the 29th annual international symposium on Computer architecture, May 25-29, 2002, Anchorage, Alaska
• 23: Ravindra Jejurikar , Cristiano Pereira , Rajesh Gupta, Leakage aware dynamic voltage scaling for real-time embedded systems, Proceedings of the 41st annual Design Automation Conference, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996650]
• 24: Masaaki Kondo , Hiroshi Sasaki , Hiroshi Nakamura, Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS, ACM SIGARCH Computer Architecture News, v.35 n.1, March 2007 [doi>10.1145/1241601.1241609]
• 25: Yongpan Liu , Huazhong Yang , Robert P. Dick , Hui Wang , Li Shang, Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems, Proceedings of the 8th International Symposium on Quality Electronic Design, p.204-209, March 26-28, 2007 [doi>10.1109/ISQED.2007.158]
• 26: Zhijian Lu , Jason Hein , Marty Humphrey , Mircea Stan , John Lach , Kevin Skadron, Control-theoretic dynamic frequency and voltage scaling for multimedia workloads, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France [doi>10.1145/581630.581654]
• 27: Mistry, K. Armstrong, M. Auth, C. Cea, S. Coan, T. Ghani, T. Hoffmann, T. Murthy, A. Sandford, J. Shaheed, R. Zawadzki, K. Zhang, K. Thompson, S. Bohr, M. Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology, Symposium on VLSI Technology, p. 50, (2004).
• 28: Christian Poellabauer, Tao Zhang, Santosh Pande, and Karsten Schwan, An Efficient Frequency Scaling Approach for Energy-Aware Embedded Real-Time Systems, Proceedings of the International Conference on Architecture of Computing Systems (ARCS'05), Innsbruck, Austria, March 2005.
• 29: Eric Rotenberg, Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 30: Greg Semeraro , David H. Albonesi , Steven G. Dropsho , Grigorios Magklis , Sandhya Dwarkadas , Michael L. Scott, Dynamic frequency and voltage control for a multiple clock domain microarchitecture, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 31: John Paul Shen, Lost in the Bermuda Triangle: Complexity vs Energy vs Performance, WCED, June 18, 2006. http://www.csl.cornell.edu/~albonesi/wced06/shen.pdf
• 32: Kevin Skadron , Tarek Abdelzaher , Mircea R. Stan, Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management, University of Virginia, Charlottesville, VA, 2001
• 33: David C. Snowdon, Sergio Ruocco and Gernot Heiser, Power Management and Dynamic Voltage Scaling: Myths and Facts, Proceedings of the 2005 Workshop on Power Aware Real-time Computing, New Jersey, USA, September, 2005
• 34: P. Stanley-Marbell and M. Hsiao and U. Kremer, A Hardware Architecture for Dynamic Performance and Energy Adaptation, In PACS-02, in conjunction with 8th IEEE International Symposium on High-Performance Computer Architecture.
• 35: Jinho Suh and Michel Dubois, Dynamic MIPS Stabilization in Out-of-Order Processors, USC Computer Engineering Technical Report CENG-2009-1, 2009.
• 36: Yudong Tan , Vincent J. Mooney III, Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches, Proceedings of the conference on Design, automation and test in Europe, p.21034, February 16-20, 2004
• 37: Ankush Varma , Brinda Ganesh , Mainak Sen , Suchismita Roy Choudhury , Lakshmi Srinivasan , Jacob Bruce, A control-theoretic approach to dynamic voltage scheduling, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA [doi>10.1145/951710.951744]
• 38: C Xu, TM Le, TT Lay, H.264/AVC CODEC: Instruction Level Complexity Analysis. Ninth IASTED International Conference on Internet and Multimedia Systems and Applications; Honolulu, HI; USA; 15--17 Aug. 2005.
• 39: Feedback EDF Scheduling Exploiting Dynamic Voltage Scaling, Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium, p.84, May 25-28, 2004
• 40: Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566451]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Performance attributes; Design studies

General Terms:
Design, Performance

Keywords:
embedded systems, ooo processors, real-time systems, stabilization, variability