Scalable high performance main memory system using phase-change memory technology

ABSTRACT

The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints.

In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

REFERENCES

• 1: The Basics of Phase Change Memory Technology. http://www.numonyx.com/Documents/WhitePapers/PCM Basics WP.pdf.
• 2: International Technology Roadmap for Semiconductors, ITRS 2007.
• 3: Apple Computer Inc. Apple Products. http://www.apple.com.
• 4: F. Bedeschil et al. A multi-level-cell bipolar-selected phase-change memory. In 2008 IEEE International Solid-State Circuits Conference, Feb. 2008.
• 5: E. Doller. Flash Memory Trends and Technologies. Intel Developer Forum, 2006.
• 6: E. Grochowski , R. D. Halem, Technological impact of magnetic hard disk drives on storage systems, IBM Systems Journal, v.42 n.2, p.338-346, April 2003
• 7: Magnus Ekman , Per Stenstrom, A case for multi-level main memory, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.1-8, June 20-20, 2004, Munich, Germany [doi>10.1145/1054943.1054944]
• 8: Magnus Ekman , Per Stenstrom, A Cost-Effective Main Memory Organization for Future Servers, Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers, p.45.1, April 04-08, 2005 [doi>10.1109/IPDPS.2005.12]
• 9: R. F. Freitas , W. W. Wilcke, Storage-class memory: the next storage system technology, IBM Journal of Research and Development, v.52 n.4, p.439-447, July 2008
• 10: HP. Memory technology evolution: an overview of system memory technologies, technology brief, 7th edition, 1999.
• 11: C.-G. Hwang. Semiconductor memories for IT era. In 2002 IEEE International Solid-State Circuits Conference, pages 24--27, Feb. 2002.
• 12: J. Javanifard et al. A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed. In 2008 IEEE International Solid--State Circuits Conference.
• 13: Taeho Kgil , David Roberts , Trevor Mudge, Improving NAND Flash Based Disk Caches, Proceedings of the 35th International Symposium on Computer Architecture, p.327-338, June 21-25, 2008
• 14: K. J. Lee et al. A 90nm 1.8V 512Mb Diode-Switch PRAM with 266 MB/s Read Throughput. isscc08, 43(1):150--162, 2008.
• 15: Charles Lefurgy , Karthick Rajamani , Freeman Rawson , Wes Felter , Michael Kistler , Tom W. Keller, Energy Management for Commercial Servers, Computer, v.36 n.12, p.39-48, December 2003 [doi>10.1109/MC.2003.1250880]
• 16: M-Systems. TrueFFS Wear-leveling Mechanism. http://www.dataio.com/pdf/NAND/MSystems/TrueFFS Wear Leveling Mechanism.pdf.
• 17: Philip Machanick, The case for SRAM main memory, ACM SIGARCH Computer Architecture News, v.24 n.5, p.23-30, Dec. 1996 [doi>10.1145/242694.242709]
• 18: J. McCalpin. Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, Dec. 1995.
• 19: MetaRAM, Inc. MetaRAM. http://www.metaram.com/.
• 20: Micron. Micron System Power Calculator. http://www.micron.com/support/part info/powercalc.
• 21: D. Nobunagal et al. A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface. In 2008 IEEE International Solid-State Circuits Conference.
• 22: S. R. Ovshinsky. Reversible electrical switching phenomena in disordered structures. Phys. Rev. Lett., 21(20), 1968.
• 23: S. Raoux , G. W. Burr , M. J. Breitwisch , C. T. Rettner , Y.-C. Chen , R. M. Shelby , M. Salinga , D. Krebs , S.-H. Chen , H.-L. Lung , C. H. Lam, Phase-change random access memory: a scalable technology, IBM Journal of Research and Development, v.52 n.4, p.465-479, July 2008
• 24: J. Tominaga, T. Kikukawa, M. Takahashi, and R. T. Phillips. Structure of the Optical Phase Change Memory Alloy, AgVInSbTe, Determined by Optical Spectroscopy and Electron Diffraction,. J. Appl. Phys., 82(7), 1997.
• 25: C. Weissenberg. Current&Future Main Memory Technology for IA Platforms. Intel Developer Forum, 2006.
• 26: N. Yamada, E. Ohno, K. Nishiuchi, and N. Akahira. Rapid-Phase Transitions of GeTe-Sb2Te3 Pseudobinary Amorphous Thin Films for an Optical Disk Memory. J. Appl. Phys., 69(5), 1991.
• 27: D. Ye et al. Prototyping a hybrid main memory using a virtual machine monitor. In Proceedings of the IEEE International Conference on Computer Design, 2008.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Dynamic memory (DRAM)

General Terms:
Design, Performance, Reliability

Keywords:
dram caching, phase change memory, wear leveling