Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors

ABSTRACT

Temperature-induced reliability issues are among the major challenges for multicore architectures. Thermal hot spots and thermal cycles combine to degrade reliability. This research presents new reliability-aware job scheduling and power management approaches for chip multiprocessors. Accurate evaluation of these policies requires a novel simulation framework that can capture architecture-level effects over tens of seconds or longer, while also capturing thermal interactions among cores resulting from dynamic scheduling policies. Using this framework and a set of new thermal management policies, this work shows that techniques that offer similar performance, energy, and even peak temperature can differ significantly in their effects on the expected processor lifetime.

REFERENCES

• 1: M. Van Biesbrouck , T. Sherwood , B. Calder, A co-phase matrix to guide simultaneous multithreading simulation, Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, p.45-56, March 10-12, 2004
• 2: N.L. Binkert, E.G. Hallnor, and S.K. Reinhardt. Network-oriented full-system simulation using M5. In Computer Architecture Evaluation using Commercial Workloads (CAECW), 2003.
• 3: P. Bose. Power-efficient microarchitectural choices at the early design stage. In Keynote Address, Workshop on Power-Aware Computer Systems, 2003.
• 4: David Brooks , Margaret Martonosi, Dynamic Thermal Management for High-Performance Microprocessors, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.171, January 20-24, 2001
• 5: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 6: D.C. Burger and T.M. Austin. The simplescalar tool set, version 2.0. Technical Report CS TR-97-1342, University of Wisconsin, Madison, June 1997.
• 7: Jichuan Chang , Gurindar S. Sohi, Cooperative cache partitioning for chip multiprocessors, Proceedings of the 21st annual international conference on Supercomputing, June 17-21, 2007, Seattle, Washington [doi>10.1145/1274971.1275005]
• 8: Ayse Kivilcim Coskun , Tajana Simunic Rosing , Keith Whisnant, Temperature aware task scheduling in MPSoCs, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 9: Gaurav Dhiman , Tajana Simunic Rosing, Dynamic voltage frequency scaling for multi-tasking systems using online learning, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA [doi>10.1145/1283780.1283825]
• 10: J. Donald and M. Martonosi. Leveraging simultaneous multithreading for adaptive thermal control. In Second Workshop on Temperature-Aware Computer Systems, 2005.
• 11: James Donald , Margaret Martonosi, Techniques for Multicore Thermal Management: Classification and New Exploration, Proceedings of the 33rd annual international symposium on Computer Architecture, p.78-88, June 17-21, 2006
• 12: Mohamed Gomaa , Michael D. Powell , T. N. Vijaykumar, Heat-and-run: leveraging SMT and CMP to manage power density through the operating system, Proceedings of the 11th international conference on Architectural support for programming languages and operating systems, October 07-13, 2004, Boston, MA, USA
• 13: S. Gunther, F. Binns, D.M. Carmean, and J.C. Hall. Managing the impact of increasing microprocessor power consumption. In Intel Technology Journal, 2001.
• 14: Seongmoo Heo , Kenneth Barr , Krste Asanović, Reducing power density through activity migration, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871561]
• 15: Intel pentium 4 processor in the 423-pin package thermal design guidelines. Technical Report 249203-001, Intel, November 2000.
• 16: Ravi Iyer , Li Zhao , Fei Guo , Ramesh Illikkal , Srihari Makineni , Don Newell , Yan Solihin , Lisa Hsu , Steve Reinhardt, QoS policies and architecture for cache/memory in CMP platforms, Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, June 12-16, 2007, San Diego, California, USA
• 17: Failure mechanisms and models for semiconductor devices, JEDEC publication JEP122C. http://www.jedec.org.
• 18: A. Karlin, M. Manesse, L. McGeoch, and S. Owicki. Competitive randomized algorithms for nonuniform problems. In Algorithmica, pages 542--571, 1994.
• 19: Amit Kumar , Li Shang , Li-Shiuan Peh , Niraj K. Jha, HybDTM: a coordinated hardware-software approach for dynamic thermal management, Proceedings of the 43rd annual Design Automation Conference, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147052]
• 20: Rakesh Kumar , Dean M. Tullsen , Norman P. Jouppi, Core architecture optimization for heterogeneous chip multiprocessors, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA [doi>10.1145/1152154.1152162]
• 21: Rakesh Kumar , Victor Zyuban , Dean M. Tullsen, Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, Proceedings of the 32nd annual international symposium on Computer Architecture, p.408-419, June 04-08, 2005
• 22: Srinivasan Murali , Almir Mutapcic , David Atienza , Rajesh Gupta , Stephen Boyd , Luca Benini , Giovanni De Micheli, Temperature control of high-performance multi-core platforms using convex optimization, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403405]
• 23: H. Nguyen. Multilevel interconnect reliability on the effects of electro-thermomechanical stresses. Ph.D. dissertation, University of Twente, Netherlands, 2004.
• 24: Michael D. Powell , Ethan Schuchman , T. N. Vijaykumar, Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.294-304, November 12-16, 2005, Barcelona, Spain [doi>10.1109/MICRO.2005.14]
• 25: Tajana Simunic Rosing , Kresimir Mihic , Giovanni De Micheli, Power and reliability management of SoCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.391-403, April 2007 [doi>10.1109/TVLSI.2007.895245]
• 26: Timothy Sherwood , Erez Perelman , Greg Hamerly , Brad Calder, Automatically characterizing large scale program behavior, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
• 27: Kevin Skadron, Hybrid Architectural Dynamic Thermal Management, Proceedings of the conference on Design, automation and test in Europe, p.10010, February 16-20, 2004
• 28: Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-aware microarchitecture, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 29: J. E. Smith, Characterizing computer performance with a single number, Communications of the ACM, v.31 n.10, p.1202-1206, Oct. 1988 [doi>10.1145/63039.63043]
• 30: Jayanth Srinivasan , Sarita V. Adve , Pradip Bose , Jude A. Rivers, The Case for Lifetime Reliability-Aware Microprocessors, ACM SIGARCH Computer Architecture News, v.32 n.2, p.276, March 2004
• 31: Jayanth Srinivasan , Sarita V. Adve , Pradip Bose , Jude A. Rivers, The Impact of Technology Scaling on Lifetime Reliability, Proceedings of the 2004 International Conference on Dependable Systems and Networks, p.177, June 28-July 01, 2004
• 32: Jayanth Srinivasan , Sarita V. Adve , Pradip Bose , Jude A. Rivers, Lifetime Reliability: Toward an Architectural Solution, IEEE Micro, v.25 n.3, p.70-80, May 2005 [doi>10.1109/MM.2005.54]
• 33: Haihua Su , Frank Liu , Anirudh Devgan , Emrah Acar , Sani Nassif, Full chip leakage estimation considering power supply and temperature variations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871529]
• 34: D. Tarjan, S. Thoziyoor, and N.P. Jouppi. CACTI 4.0. Technical Report HPL-2006-86, HP Laboratories Palo Alto, 2006.
• 35: Qiang Wu , Margaret Martonosi , Douglas W. Clark , V. J. Reddi , Dan Connors , Youfeng Wu , Jin Lee , David Brooks, A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.271-282, November 12-16, 2005, Barcelona, Spain [doi>10.1109/MICRO.2005.7]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Modeling techniques

General Terms:
Reliability

Keywords:
chip multiprocessors, reliability, simulation methodology, thermal management