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On approximating the ideal random access machine by physical machines
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Journal of the ACM (JACM) archive
Volume 56 ,  Issue 5  (August 2009) table of contents
Article No. 27  
Year of Publication: 2009
ISSN:0004-5411
Authors
Gianfranco Bilardi  Università di Padova, Padova, Italy
Kattamuri Ekanadham  IBM T.J.Watson Research Center, Yorktown Heights, NY
Pratap Pattnaik  IBM T.J.Watson Research Center, Yorktown Heights, NY
Publisher
ACM  New York, NY, USA
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ABSTRACT

The capability of the Random Access Machine (RAM) to execute any instruction in constant time is not realizable, due to fundamental physical constraints on the minimum size of devices and on the maximum speed of signals. This work explores how well the ideal RAM performance can be approximated, for significant classes of computations, by machines whose building blocks have constant size and are connected at a constant distance.

A novel memory structure is proposed, which is pipelined (can accept a new request at each cycle) and hierarchical, exhibiting optimal latency a(x) = O(x1/d) to address x, in d-dimensional realizations.

In spite of block-transfer or other memory-pipeline capabilities, a number of previous machine models do not achieve a full overlap of memory accesses. These are examples of machines with explicit data movement. It is shown that there are direct-flow computations (without branches and indirect accesses) that require time superlinear in the number of instructions, on all such machines.

To circumvent the explicit-data-movement constraints, the Speculative Prefetcher (SP) and the Speculative Prefetcher and Evaluator (SPE) processors are developed. Both processors can execute any direct-flow program in linear time. The SPE also executes in linear time a class of loop programs that includes many significant algorithms. Even quicksort, a somewhat irregular, recursive algorithm admits a linear-time SPE implementation. A relation between instructions called address dependence is introduced, which limits memory-access overlap and can lead to superlinear time, as illustrated with the classical merging algorithm.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Abolhassan, F., Drefenstedt, R., Keller, J., Paul, W. J., and Scheerer, D. 1993. On the physical design of prams. Comput. J. 36, 8, 756--762.
2
 
3
 
4
 
5
Alpern, B., Carter, L., Feig, E., and Selker, T. 1994. The uniform memory hierarchy model of computation. Algorithmica 12, 2/3, 72--109.
6
 
7
8
9
10
 
11
 
12
 
13
 
14
 
15
16
 
17
Cook, S. A., and Reckhow, R. A. 1973. Time-bounded random access machines. J. Comput. Syst. Sci. 7, 4, 354--375.
18
 
19
 
20
21
 
22
 
23
 
24
Luccio, F., and Pagli, L. 1993. A model of sequential computation with pipelined access to memory. Math. Syst. Theory 26, 4, 343--356.
 
25
Mattson, R. L., Gecsei, J., Slutz, D. R., and Traiger, I. L. 1970. Evaluation techniques for storage hierarchies. IBM Syst. J. 9, 2, 78--117.
 
26
Metcalf, C. 1993. Data prefetching: A cost/performance analysis. Area Exam, MIT, Cambridge.
 
27
 
28
Polychronopoulos, C. 1987. Loop coalescing: A compiler transformation for parallel machines. In Proceedings of the International Conference on Parallel Processing. 235--242.
 
29
 
30
 
31
Smith, B. J. 1981. Architecture and applications of the HEP multiprocessor system. In Real-Time Signal Processing IV. vol. 298. 241--248.
 
32
Valiant, L. G. 1990. General purpose parallel architectures. Elsevier-MIT Press, Amsterdam, The Netherlands.
 
33
 
34
von Neumann, J. 1945. First draft of a report on the EDVAC. http://www.virtualtravelog.net/enteries/2003-08-TheFirstDraft.pdf.
 
35
Whaley, R. C., and Dongarra, J. J. 1998. Automatically Tuned Linear Algebra Software. http://www.netlib.org/atlas/index.html.
36
 
37
38
39

Collaborative Colleagues:
Gianfranco Bilardi: colleagues
Kattamuri Ekanadham: colleagues
Pratap Pattnaik: colleagues