| Programming model for a heterogeneous x86 platform |
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Conference on Programming Language Design and Implementation
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Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
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Dublin, Ireland
SESSION: Parallelism, performance, and traces
table of contents
Pages 431-440
Year of Publication: 2009
ISBN:978-1-60558-392-1
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Authors
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Bratin Saha
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Intel Corporation, Santa Clara, USA
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Xiaocheng Zhou
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Intel Corporation, Beijing, China
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Hu Chen
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Intel Corporation, Beijing, China
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Ying Gao
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Intel Corporation, Beijing, China
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Shoumeng Yan
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Intel Corporation, Beijing, China
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Mohan Rajagopalan
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Intel Corporation, Santa Clara, USA
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Jesse Fang
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Intel Corporation, Santa Clara, USA
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Peinan Zhang
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Intel Corporation, Santa Clara, USA
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Ronny Ronen
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Intel Corporation, Haifa, Israel
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Avi Mendelson
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Microsoft Corporation, Haifa, Israel
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ABSTRACT
The client computing platform is moving towards a heterogeneous architecture consisting of a combination of cores focused on scalar performance, and a set of throughput-oriented cores. The throughput oriented cores (e.g. a GPU) may be connected over both coherent and non-coherent interconnects, and have different ISAs. This paper describes a programming model for such heterogeneous platforms. We discuss the language constructs, runtime implementation, and the memory model for such a programming environment. We implemented this programming environment in a x86 heterogeneous platform simulator. We ported a number of workloads to our programming environment, and present the performance of our programming environment on these workloads.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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