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Towards device emulation code generation
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Language, Compiler and Tool Support for Embedded Systems archive
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems table of contents
Dublin, Ireland
SESSION: Architecture and multicores table of contents
Pages 109-118  
Year of Publication: 2009
ISBN:978-1-60558-356-3
Also published in ...
Authors
Thomas Heinz  Robert Bosch GmbH, Stuttgart, Germany
Reinhard Wilhelm  Saarland University, Saarbrücken, Germany
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGART: ACM Special Interest Group on Artificial Intelligence
SIGPLAN: ACM Special Interest Group on Programming Languages
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

For non-embedded software, binary translation has shown to be a successful method for retargeting legacy software onto new platforms. To apply binary translation to embedded software, two issues must be considered. First of all, embedded software often involves real-time constraints that must still be met after translation. Secondly, embedded software contains a significant amount of code dedicated to peripheral device communication which necessitates device emulation. This paper focuses on the last aspect.

Usually, device emulation code is handcrafted which is tedious and error-prone. This paper presents a method to automatically generate device emulation code from a formal specification of source and target device operations. At the heart of the device operation semantics lie quantifier-free formulae in the theory of fixed width bit vector arithmetic which is a decidable fragment of first-order logic. To the best of our knowledge, this is the first attempt to generate device emulation code from a formal specification.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Sorav Bansal and Alex Aiken. Binary translation using peephole superoptimizers. In ph8th USENIX Symposium on Operating System Design and Implementation (OSDI 2008), December 2008.
2
 
3
Clark Barrett and Cesare Tinelli. CVC3. In Werner Damm and Holger Hermanns, editors, phProceedings of the 19th International Conference on Computer Aided Verification (CAV'07), volume 4590 of phLecture Notes in Computer Science, pages 298--302. Springer-Verlag, July 2007. Berlin, Germany.
 
4
Clark Barrett, Roberto Sebastiani, Sanjit Seshia, and Cesare Tinelli. Satisfiability modulo theories. In Armin Biere, Hans van Maaren, and Toby Walsh, editors, phHandbook of Satisfiability, volume 4, chapter 8. IOS Press, February 2009. ISBN 978-1-58603-929-5.
 
5
 
6
Marco Benedetti and Hratch Mangassarian. QBF-based formal verification: Experience and perspectives. phJournal on Satisability, Boolean Modeling and Computation, 5: 133--191, 2008.
 
7
 
8
Randal E. Bryant, Daniel Kroening, Joël Ouaknine, Sanjit A. Seshia, Ofer Strichman, and Bryan Brady. Deciding bit-vector arithmetic with abstraction. In phProc. TACAS 2007, March 2007.
 
9
 
10
 
11
Bryce Howard Cogswell. Timing insensitive binary-to-binary translation. PhD thesis, Carnegie Mellon University, Pittsburgh, Pennsylvania 15213, April 1995.
12
 
13
Patrick Cousot and Radhia Cousot. Static determination of dynamic properties of programs. In phProceedings of the Second International Symposium on Programming, pages 106--130. Dunod, Paris, France, 1976.
 
14
Leonardo de Moura and Nikolaj Bjørner. Z3: An efficient SMT solver. In Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), volume 4963 of Lecture Notes in Computer Science, pages 337--340. Springer, 2008.
 
15
 
16
Vijay Ganesh and David L. Dill. A decision procedure for bit-vectors and arrays. In Computer Aided Verification (CAV'07), Berlin, Germany, July 2007. Springer-Verlag.
 
17
 
18
 
19
 
20
 
21
Manish Prasad and Tzi-cker Chiueh. A binary rewriting defense against stack-based buffer overflow attacks. In Proceedings of the USENIX Annual Technical Conference, pages 211--224, 2003.
 
22
23
24
 
25
Henrik Theiling. phControl Flow Graphs For Real-Time Systems Analysis. PhD thesis, Saarland University, 2002.
 
26
er(2004)}troeger_bintransJens Tröger. Specification-Driven Dynamic Binary Translation. PhD thesis, Queensland University of Technology, Brisbane, Australia, December 2004.
 
27
Reinhard Wilhelm. Determining bounds on execution times. In R. Zurawski, editor, phHandbook on Embedded Systems, pages 14--1, 14-23. CRC Press, 2005.
 
28
Lea Wittie, Chris Hawblitzel, and Derrin Pierret. Generating a statically-checkable device driver I/O interface. In phProceedings of the Workshop on Automatic Program Generation for Embedded Systems (APGES), October 2007.

Collaborative Colleagues:
Thomas Heinz: colleagues
Reinhard Wilhelm: colleagues