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Load balancing using work-stealing for pipeline parallelism in emerging applications
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International Conference on Supercomputing archive
Proceedings of the 23rd international conference on Supercomputing table of contents
Yorktown Heights, NY, USA
POSTER SESSION: Posters table of contents
Pages 517-518  
Year of Publication: 2009
ISBN:978-1-60558-498-0
Authors
Angeles Navarro  University of Malaga, Malaga, Spain
Rafael Asenjo  University of Malaga, Malaga, Spain
Siham Tabik  University of Malaga, Malaga, Spain
Cǎlin Caşcaval  IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

Parallel programming is a requirement in the multi-core era. One of the most promising techniques to make parallel programming available for general users is the use of parallel programming patterns. Functional pipeline parallelism is a well suited pattern for many emerging applications, such as streaming and "Recognition, Mining and Synthesis" (RMS) workloads. In this paper we develop an analytical model for pipeline parallelism and use it to characterize and optimize two of the PARSEC benchmarks which use the parallel pipeline pattern, ferret and dedup. We identify two scalability limitations: load imbalance and I/O bottlenecks. We address load imbalance using two techniques: parallel pipeline stage collapsing and dynamic scheduling. We implemented these optimizations using Pthreads and the Threading Building Blocks (TBB) libraries. We compare predicted and measured performance of all these implementations on a large scale SMP machine and we note that the work-stealing TBB implementation outperforms all other variants.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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G. Contreras and M. Martonosi. Characterizing and improving the performance of intel threading building blocks. In Workload Characterization, 2008. IISWC 2008. IEEE International Symposium on, pages 57--66, Sept. 2008.
 
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A. Navarro, R. Asenjo, S. Tabik, and C. Cascaval. Load Balancing using Work-Stealing for Pipeline Parallelism in Emerging Applications. Technical report, Dept. of Computer Architecture. Univ. of Malaga, 2009. http://www.ac.uma.es/ asenjo/research/.
 
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Collaborative Colleagues:
Angeles Navarro: colleagues
Rafael Asenjo: colleagues
Siham Tabik: colleagues
Cǎlin Caşcaval: colleagues