TransMetric

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

TransMetric: architecture independent workload characterization for transactional memory benchmarks

Full text

Pdf (849 KB)

Source

International Conference on Supercomputing archive
Proceedings of the 23rd international conference on Supercomputing table of contents

Yorktown Heights, NY, USA

POSTER SESSION: Posters table of contents

Pages 491-492

Year of Publication: 2009

ISBN:978-1-60558-498-0

Authors

James Poe	University of Florida, Gainesville, FL, USA
Clay Hughes	University of Florida, Gainesville, FL, USA
Tao Li	University of Florida, Gainesville, FL, USA

Sponsors

ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 33, Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1542275.1542345 What is a DOI?

ABSTRACT

Transactional memory (TM) has emerged as a parallel programming paradigm for multi-core processors yet there is no standardized set of metrics with which to describe their behavior. In this work, we propose a set of transaction-oriented workload characteristics that can accurately capture the behavior of transactional memory programs. We apply principle component analysis and clustering algorithms to analyze the proposed transactional workload characteristics and show that these characteristics are architecturally independent

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Maurice Herlihy , J. Eliot B. Moss, Transactional memory: architectural support for lock-free data structures, ACM SIGARCH Computer Architecture News, v.21 n.2, p.289-300, May 1993
	2	Jayaram Bobba , Kevin E. Moore , Haris Volos , Luke Yen , Mark D. Hill , Michael M. Swift , David A. Wood, Performance pathologies in hardware transactional memory, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	3	Austen McDonald , JaeWoong Chung , Hassan Chafi , Chi Cao Minh , Brian D. Carlstrom , Lance Hammond , Christos Kozyrakis , Kunle Olukotun, Characterization of TCC on Chip-Multiprocessors, Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, p.63-74, September 17-21, 2005 [doi>10.1109/PACT.2005.11]
	4	James Poe , Chang-Burm Cho , Tao Li, Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design, Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing, p.159-166, October 29-November 01, 2008 [doi>10.1109/SBAC-PAD.2008.18]