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Dynamic parallelization of single-threaded binary programs using speculative slicing
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International Conference on Supercomputing archive
Proceedings of the 23rd international conference on Supercomputing table of contents
Yorktown Heights, NY, USA
SESSION: Compilers table of contents
Pages 158-168  
Year of Publication: 2009
ISBN:978-1-60558-498-0
Authors
Cheng Wang  Intel Corporation, Santa Clara, CA, USA
Youfeng Wu  Intel Corporation, Santa Clara, CA, USA
Edson Borin  Intel Corporation, Santa Clara, CA, USA
Shiliang Hu  Intel Corporation, Santa Clara, CA, USA
Wei Liu  Intel Corporation, Santa Clara, CA, USA
Dave Sager  Intel Corporation, Hillsboro, OR, USA
Tin-fook Ngai  Intel Corporation, Santa Clara, CA, USA
Jesse Fang  Intel Corporation, Santa Clara, CA, USA
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

The performance of single-threaded programs and legacy binary code is of critical importance in many everyday applications. However, neither can hardware multi-core processors directly speed up single-threaded programs, nor can software automatic parallelizing compilers effectively parallelize legacy binary code and irregular applications. In this paper, we propose a framework and a set of algorithms to dynamically parallelize single-threaded binary programs. Our parallelization is based on program slicing and explores both instruction-level parallelism (ILP) and thread-level parallelism (TLP). To significantly reduce the critical path of the parallel slices, our slicing algorithms exploit speculation to cut rare dependences, and use well-designed program transformations to expose parallelism. Furthermore, because we transparently parallelize binary code at runtime, we perform slicing only on program hot regions. Our experiments demonstrate that the proposed speculative slicing approach extracts more parallelism than any known slicing based parallelization schemes. For the SPEC2000 benchmarks, we can achieve 3x parallelism with infinite number of threads, and 1.8x parallelism with 4 threads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Cheng Wang: colleagues
Youfeng Wu: colleagues
Edson Borin: colleagues
Shiliang Hu: colleagues
Wei Liu: colleagues
Dave Sager: colleagues
Tin-fook Ngai: colleagues
Jesse Fang: colleagues