| Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic |
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International Conference On Simulation Tools And Techniques For Communications, Networks And Systems & Workshops
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Proceedings of the 2nd International Conference on Simulation Tools and Techniques
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Rome, Italy
SESSION: Simulation of hardware
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Article No. 23
Year of Publication: 2009
ISBN:978-963-9799-45-5
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Downloads (6 Weeks): 17, Downloads (12 Months): 42, Citation Count: 0
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ABSTRACT
Performance of two network-on-chip (NoC) topologies is compared for the use in multicore processors. The performance evaluation is supported by the CINSim simulator. This simulator has been developed to model a variety of network topologies that are based on atomic components such as buffers, routers, traffic generators, and target buffers. The development of this simulator was driven by the investigation of networks-on-chip. But off-chip networks can be examined as well. Two examples for NoC topologies, a mesh and a bidirectional interconnection network, are compared. Unicast traffic is used as well as multicast and local traffic, which both represent a significant part of the network traffic for evaluating multi-core processors. In addition to the performance, the mean distance, the diameter, and the buffer cost are calculated for both network topologies. The results show that bidirectional multistage interconnection networks outperform meshes. A clearly better scalability is shown by the bidirectional multistage interconnection networks.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Monica Alderighi , Fabio Casini , Sergio D'Angelo , Davide Salvi , Giacomo R. Sechi, A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications, Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), p.302, January 29-31, 2002
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2
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3
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Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005
[doi> 10.1109/TPDS.2005.22]
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6
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9
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10
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D. Lüdtke, D. Tutsch, A. Walter, and G. Hommel. Improved performance of bidirectional multistage interconnection networks by reconfiguration. In Proceedings of 2005 Design, Analysis, and Simulation of Distributed Systems (DASD 2005); San Diego, pages 21--27. SCS, Apr. 2005.
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11
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12
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| |
13
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P. P. Pande, C. S. Grecu, A. Ivanov, and R. A. Saleh. Switch-based interconnect architecture for future systems on chip. In Proceedings of the SPIE, volume 5117, pages 228--237, 2003.
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14
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Stergios Stergiou , Federico Angiolini , Salvatore Carta , Luigi Raffo , Davide Bertozzi , Giovanni De Micheli, ×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips, Proceedings of the conference on Design, Automation and Test in Europe, p.1188-1193, March 07-11, 2005
[doi> 10.1109/DATE.2005.1]
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15
|
|
| |
16
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Y. Yang and J. Wang. A class of multistage conference switching networks for group communication. IEEE Transactions on Parallel and Distributed Systems, 15(3):228--243, Mar. 2004.
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