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Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic
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Source International Conference On Simulation Tools And Techniques For Communications, Networks And Systems & Workshops archive
Proceedings of the 2nd International Conference on Simulation Tools and Techniques table of contents
Rome, Italy
SESSION: Simulation of hardware table of contents
Article No. 23  
Year of Publication: 2009
ISBN:978-963-9799-45-5
Authors
Dietmar Tutsch  Bergische Universität Wuppertal, Wuppertal, Germany
Miroslaw Malek  Humboldt-Universität zu Berlin, Berlin, Germany
Sponsors
: Create-Net
: ICST
Publisher
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DOI Bookmark: 10.4108/ICST.SIMUTOOLS2009.5590

ABSTRACT

Performance of two network-on-chip (NoC) topologies is compared for the use in multicore processors. The performance evaluation is supported by the CINSim simulator. This simulator has been developed to model a variety of network topologies that are based on atomic components such as buffers, routers, traffic generators, and target buffers. The development of this simulator was driven by the investigation of networks-on-chip. But off-chip networks can be examined as well. Two examples for NoC topologies, a mesh and a bidirectional interconnection network, are compared. Unicast traffic is used as well as multicast and local traffic, which both represent a significant part of the network traffic for evaluating multi-core processors. In addition to the performance, the mean distance, the diameter, and the buffer cost are calculated for both network topologies. The results show that bidirectional multistage interconnection networks outperform meshes. A clearly better scalability is shown by the bidirectional multistage interconnection networks.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Dietmar Tutsch: colleagues
Miroslaw Malek: colleagues