Modeling networking issues of network-on-chip

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Modeling networking issues of network-on-chip: a coloured petri nets approach

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International Conference On Simulation Tools And Techniques For Communications, Networks And Systems & Workshops archive
Proceedings of the 2nd International Conference on Simulation Tools and Techniques table of contents

Rome, Italy

SESSION: Simulation of hardware table of contents

Article No. 22

Year of Publication: 2009

ISBN:978-963-9799-45-5

Authors

Hamid Hajabdolali Bazzaz	University of Tehran, Tehran, Iran
Marjan Sirjani	University of Tehran, Tehran, Iran and Reykjavik University, Reykjavik, Iceland
Ramtin Khosravi	University of Tehran, Tehran, Iran
Shamim Taheri	University of Tehran, Tehran, Iran

Sponsors

: Create-Net
: ICST

Publisher

ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering) ICST, Brussels, Belgium, Belgium

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Downloads (6 Weeks): 7, Downloads (12 Months): 33, Citation Count: 0

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DOI Bookmark:	10.4108/ICST.SIMUTOOLS2009.5574

ABSTRACT

Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-on-a-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification of these on-chip algorithms, in this paper, we propose a detailed NoC CPN model in which key NoC networking challenges, namely network topology, switching method, and routing algorithm are considered. By this model, any desired NoC topologies, including but not limited to, mesh and k-ary n-cube can be constructed. As for switching techniques, dominant on-chip switching methods, namely, packet switching, circuit switching, and wormhole switching, are modeled. Besides, as model of a NoC switch element is highly dependent on its switch fabric type, different sorts of switching fabrics, i.e., crossbar and shared bus, are modeled in this contribution. For routing the packets between cores, a CPN version of dimension-ordered routing, dominant routing algorithm for NoC, is implemented in the switches.

REFERENCES

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