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Statistical analysis of circuit timing using majorization
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Communications of the ACM archive
Volume 52 ,  Issue 8  (August 2009) table of contents
A Blind Person's Interaction with Technology
SECTION: Research highlights table of contents
Pages 95-100  
Year of Publication: 2009
ISSN:0001-0782
Authors
Michael Orshansky  University of Texas, Austin
Wei-Shen Wang  Mentor Graphics, Taipei, Taiwan
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Agarwal, A., Zolotov, V., Blaauw, D.T. Statistical timing analysis using bounds and selective enumeration. IEEE Trans. Comp. Aided Des. Integr. Circuits Syst. 22, 9 (2003), 1243--1260.
 
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Jyu, H.F., Malik, S., Devadas, S., Keutzer, K.W. Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1, 2 (1993), 126--137.
 
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Marshall, A.W., Olkin, I. Inequalities: Theory of Majorization and Its Applications. Academic Press, New York, 1979.
 
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Moretti G. CLK Design Automation introduces Amber FX Analyzer, EDA Design Line. Retrieved on May 22, 2009, http://www.edadesignline.com/.
 
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Nadas, A. Probabilistic PERT. IBM J. Res. Dev. 23, 3 (1979), 339--347.
 
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Robillard, P., Trahan M. The completion time of PERT networks. Oper. Res. 25, 1 (1977), 15--29.
 
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Tong, Y.L. Probability Inequalities in Multivariate Distributions. Academic Press, New York, 1980.
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Wang, W.S., Orshansky, M. Path-based statistical timing analysis handling arbitrary delay correlations: theory and implementation. IEEE Trans. Comp. Aided Des. Integr. Circuits Syst. 25, 12 (2006), 2976--2988.
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Collaborative Colleagues:
Michael Orshansky: colleagues
Wei-Shen Wang: colleagues