TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA

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TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA

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ACM Transactions on Reconfigurable Technology and Systems (TRETS) archive
Volume 2 , Issue 2 (June 2009) table of contents

Article No.: 8

Year of Publication: 2009

ISSN:1936-7406

Authors

Weisheng Zhao	University of Paris--Sud and CNRS
Eric Belhaire	University of Paris--Sud and CNRS
Claude Chappert	University of Paris--Sud and CNRS
Bernard Dieny	SPINTEC
Guillaume Prenat	SPINTEC

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ACM New York, NY, USA

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Downloads (6 Weeks): 16, Downloads (12 Months): 149, Citation Count: 1

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ABSTRACT

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice model, some chip characteristic results such as the programming latency (~25ns) and power dissipation (~124pJ) have been calculated or simulated to demonstrate the expected performance of TAS-MRAM-based FPGA logic circuits.

REFERENCES

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