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State persistence: a property for guiding test generation
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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents
Boston Area, MA, USA
SESSION: Testing table of contents
Pages 523-528  
Year of Publication: 2009
ISBN:978-1-60558-522-2
Authors
Irith Pomeranz  Purdue University, West Lafayette, IN, USA
Sudhakar M. Reddy  University of Iowa, Iowa City, IA, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

We study a property of circuit states referred to as persistence. The persistence pi(s) of a state s is the number of next-state variables whose values are specified (0 or 1) when a fully-unspecified primary input vector is applied to the circuit in state s. When a next-state variable Yi is specified under a fully-unspecified primary input vector, there are faults in the input cone of Yi that cannot be detected on Yi. We demonstrate through experimental results that when lower-persistence states are used as scan-in states, the resulting tests detect larger numbers of faults. Low-persistence states are thus preferable as scan-in states during test generation. We also discuss the computation of low-persistence states.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J. Savir and S. Patil, "Broad-Side Delay Test", IEEE Trans. on Computer-Aided Design, Aug. 1994, pp. 1057--1064.
 
2
P. Goel and B.C. Rosales, "Test Generation and Dynamic Compaction of Tests", in Proc. Test Conf., 1979, pp. 189--192.
 
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4
J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits", in Proc. Asian Test Symp., 1992, pp. 20--25.
 
5
Y. Matsunaga, "MINT -An Exact Algorithm for Finding Minimum Test Sets", IEICE Trans. Fundamentals., vol. E76-A, No. 10, Oct. 1993, pp. 1652--1658.
 
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S. Kajihara, I. Pomeranz, K. Kinoshita and S.M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Dec. 1995, pp. 1496--1504.
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9
 
10
 
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S.Y. Lee and K.K. Saluja, "Test Application Time Reduction for Sequential Circuits with Scan", IEEE Trans. on Computer-Aided Design, Sept. 1995, pp. 1128--1140.
 
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Collaborative Colleagues:
Irith Pomeranz: colleagues
Sudhakar M. Reddy: colleagues