A power-effective scan architecture using scan flip-flops clustering and post-generation filling

ABSTRACT

In this paper, we propose a novel way to save test power, using the DFT based technique as basic method and post-generation filling as complementary. In this architecture, two methods of clustering flip-flops into scan chains are presented. One is clustering scan flip-flops into two parts to save capture power, and the other is clustering scan flip-flops of each part into scan chains to save shift power. By partitioning the scan flip-flops into two parts, the capture operation is cut into two sequential steps, which can effectively reduce the capture power. By partitioning flip-flops with common successors into one chain, we can make sure that, only one or a small part of scan chains are active during the shifting phase. For other scan chains, filling strategy is used as complementary method to further reduce test power. This architecture can effectively reduce the test time too. Experimental results show that average power reduction of 91.81% and average peak power reduction of 49.35% can be achieved, comparing to the ordinary full-scan architecture.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Reliability

Keywords:
design for test, low power, scan design, test