Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding

ABSTRACT

By storing multiple bits in each memory cell, multi-level per cell (MLC) NAND flash memories have been increasingly dominant in the flash memory market due to their obvious storage density advantage. However, MLC NAND flash memories are much more subject to storage reliability degradation as the technology continues to scale down. This paper presents an error correcting solution by concatenating trellis coded modulation (TCM) with an outer BCH code, which can greatly improve the performance compared with the current design practice that uses BCH codes only. The key is that TCM can well match to the multi-level storage characteristic in order to reduce the memory bit error rate and hence relieve the burden of outer BCH code, at no cost of extra redundant memory cells. The superior error correcting performance of such concatenated TCM-BCH coding systems for MLC NAND flash memories has been well demonstrated through computer simulations, and their silicon implementation efficiency has been evaluated through ASIC design at 65nm node.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.2 Reliability and Testing**

General Terms:
Design

Keywords:
fault-tolerance, nand flash, tcm