A switchable PLL frequency synthesizer and hot carrier effects

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A switchable PLL frequency synthesizer and hot carrier effects

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

SESSION: VLSI circuits table of contents

Pages 481-486

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Yang Liu	Louisiana State University, Baton Rouge, LA, USA
Ashok Srivastava	Louisiana State University, Baton Rouge, LA, USA
Yao Xu	Louisiana State University, Baton Rouge, LA, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 7, Downloads (12 Months): 19, Citation Count: 0

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ABSTRACT

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed, designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulation results show that the frequency range of the switchable PLL is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the PLL changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of PLL reaches as low as -61 dBc/Hz at 10 kHz offset frequency and -104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in open loop voltage-controlled oscillator (VCO). The VCO oscillation frequency decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different PLL output frequencies after 4 hours of stress time.

REFERENCES

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