Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

ABSTRACT

In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18um technology in worst case conditions(1.62V, 125 C).

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration); Algorithms implemented in hardware

General Terms:
Algorithms, Design, Performance

Keywords:
h.264, reconfigurable architecture, vlsi