Low power and high performance sram design using bank-based selective forward body bias

ABSTRACT

Leakage power consumption is a large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large portion of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45nm technology node, since these processes exhibit significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from a performance degradation standpoint. In this paper, we quantify this problem and provide a solution, using a 512KByte SRAM implemented in a 45nm bulk process as a design example. We show that implementing the SRAM as a monolithic memory results in increased delay as well as power. We illustrate a methodology to optimally reduce leakage power and improve performance in memories by splitting the memory array into word line groups (WLGs) which are selectively forward body biased when accessed. We present a derivation of optimal number of WLGs and the forward body bias voltage value, and show that our approach results in a 9:2% access time reduction, and a 53:4% reduction in power during a read operation. Our approach also achieves an 18% reduction in power during a write operation and a 69% leakage power improvement. The area overhead of our scheme is 7:2% compared to a monolithic memory.

REFERENCES

• 1: "The International Technology Roadmap for Semiconductors," http://public.itrs.net/, 2003.
• 2: "BSIM3 Homepage," http://www-device.eecs.berkeley.edu/~bsim3/arch ftp.html.
• 3: Takashi Inukai , Toshiro Hiramoto , Takayasu Sakurai, Variable threshold CMOS (VTCMOS) in series connected circuits, Proceedings of the 2001 international symposium on Low power electronics and design, p.201-206, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383133]
• 4: F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI," IEEE Transactions on Electron Devices, vol. 44, no. 3, pp. 414--422, Mar 1997.
• 5: Amit Agarwal , Hai Li , Kaushik Roy, DRG-cache: a data retention gated-ground cache for low power, Proceedings of the 39th annual Design Automation Conference, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514037]
• 6: H. Yamauchi, T. Iwata, H. Akamatsu, and A. Matsuzawa, "A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecturewith charge-recycle offset-source driving (OSD) scheme," in Symposium on VLSI Circuits, Honolulu, HI, 1996.
• 7: A. Bhavnagarwala, A. Kapoor, and J. Meindl, "Dynamic-threshold CMOS SRAM cells for fast, portable applications," in IEEE International ASIC/SOC Conference, Sept 2000, pp. 359--363.
• 8: Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor Mudge, Drowsy caches: simple techniques for reducing leakage power, Proceedings of the 29th annual international symposium on Computer architecture, May 25-29, 2002, Anchorage, Alaska
• 9: C. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations," IEEE Transactions on VLSI Systems, vol. 13, no. 3, pp. 349--357, 2005.
• 10: Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, Proceedings of the 29th annual international symposium on Computer architecture, May 25-29, 2002, Anchorage, Alaska
• 11: I. Meta-Software, "HSPICE user's manual," Campbell, CA. "45nm SRAM Technology Development," 2006, http://www.intel.com/technology/itj/2008/v12i2/4-SRAM/3-overview.htm.
• 12: "Predictive Technology Model" http://www.eas.asu.edu/~ptm/.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Static memory (SRAM)

General Terms:
Design, Performance

Keywords:
body bias, high performance, low power