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ABSTRACT

Coarse grained arithmetic and logic units have long been the primary computational units for media processing. This paper presents the organization and VLSI implementation of a new 8bit, Single Instruction Multiple Data (SIMD) compatible ALU for fast, area and power efficient arithmetic and logic operations. An array of 8 such units, along with the interconnect network to perform 16 bit multiplication is shown. The array was custom implemented in IBM 0.13 CMOS process. Post layout simulation results show cell operation at 1.02GHz with a power consumption of 1.34mW. The proposed cell consumes 22-52% less power than competing architectures, while providing GHz range operating speeds. The array is found to provide almost 6 times the performance of dedicated 16 bit multiplication units, while still providing 60% power improvement. A generalized mapping scheme for implementing higher precision arithmetic operations using the proposed ALU as the basic building block is shown.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES

General Terms:
Design, Performance

Keywords:
design, performance