| Incremental buffer insertion and module resizing algorithm using geometric programming |
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Great Lakes Symposium on VLSI
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Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Boston Area, MA, USA
POSTER SESSION: Poster session 2
table of contents
Pages 413-416
Year of Publication: 2009
ISBN:978-1-60558-522-2
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Authors
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Qing Dong
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University of Kitakyushu, Kitakyushu, Japan
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Bo Yang
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University of Kitakyushu, Kitakyushu, Japan
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Jing Li
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University of Kitakyushu, Kitakyushu, Japan
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Shigetoshi Nakatake
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University of Kitakyushu, Kitakyushu, Japan
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Downloads (6 Weeks): 10, Downloads (12 Months): 26, Citation Count: 0
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ABSTRACT
This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keep the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modelled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wirelength difference between the initial floorplan and result is quite small (less than 5%), and the global structure of the initial floorplan is preserved very well.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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S. Boyd, S.-J. Kim, L. Vandenberghe, and A. Hassibi. A tutorial on geometric programming. Optimization and Engineering, (1):67--127, 2007.
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Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Mal , Yici Cai , Chung-Kuan Cheng , Jun Gu, A buffer planning algorithm based on dead space redistribution, Proceedings of the 2003 Asia and South Pacific Design Automation Conference, January 21-24, 2003, Kitakyushu, Japan
[doi> 10.1145/1119772.1119859]
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W. Chen, C. T. Hsieh, and M. Pedram. Simultaneous gate sizing and placement. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 19(2):206--214, 2000.
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Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
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