A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level models

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A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level models

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

POSTER SESSION: Poster session 2 table of contents

Pages 405-408

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Zhu Zhou	Intel Corporation, Chandler, AZ, USA
Dharmin Parikh	Intel Corporation, Chandler, AZ, USA
Pradnyesh Gudadhe	Arizona State University, Tempe, AZ, USA
Arunabha Sen	Arizona State University, Tempe, AZ, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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ABSTRACT

OSCI's TLM-2.0 standard enables the simulation of functionality and timing of a system by defining two coding styles namely Loosely-timed (LT) and approximately timed (AT). Without dynamic switching between the two modes, a user interested in performance analysis is forced to execute the model in AT mode for the entire duration of simulation. A run-time switching mechanism enables user to execute uninteresting simulation portions (e.g. operating system boot) in the high speed LT mode and switch to detailed AT model only when one needs to carry out detailed micro-architectural analysis (e.g. benchmark execution). In this paper, we introduce a comprehensive switching mechanism that addresses all the potential issues during LT-to-AT and AT-to-LT transitions. We test this switching methodology on one Intel proprietary Interconnect Bus model and demonstrate a 24X speedup over AT-only simulations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	OSCI TLM-2.0 User Manual, Open SystemC Initiative (OSCI), Version JA22, June 2008
	2	Jerome Cornet, Florence Maraninchi, Laurent Mailet-Contoz. A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of System-on-Chip.
	3	Pin-Hsien Lu. Dynamically Switching Between Hardware Abstraction Models for Rapid Embedded Software Development. Master degree thesis submitted to National Chung Cheng University, August 2006.