| Timing-driven N-way decomposition |
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Great Lakes Symposium on VLSI
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Proceedings of the 19th ACM Great Lakes symposium on VLSI
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Boston Area, MA, USA
SESSION: Logic verification and optimization
table of contents
Pages 363-368
Year of Publication: 2009
ISBN:978-1-60558-522-2
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Downloads (6 Weeks): 1, Downloads (12 Months): 21, Citation Count: 0
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ABSTRACT
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techniques to reduce the depth of the netlist due to the affordable computational cost. We present a novel n-way decomposition technique that improves bi-decomposition. The problem of decomposition is formulated as a Boolean relation which captures a larger set of possible solutions compared to bi-decomposition. The solution obtained from the Boolean relation improves the delay with near-zero cost in area. As it is shown on the experimental results, a considerable improvement is achieved on large netlists and even larger depending on which technology mapper is used.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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