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Accelerating multi-party scheduling for transaction-level modeling
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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents
Boston Area, MA, USA
SESSION: System- and architectural-level optimization table of contents
Pages 339-344  
Year of Publication: 2009
ISBN:978-1-60558-522-2
Authors
Di Wang  Boston University, Boston, MA, USA
Vyas Venkataraman  Boston University, Boston, MA, USA
Zhen Wang  Boston University, Boston, MA, USA
Wei Qin  Boston University, Boston, MA, USA
Hangsheng Wang  Freescale Semiconductor Inc., Austin, TX, USA
Mrinal Bose  Freescale Semiconductor Inc., Austin, TX, USA
Jayanta Bhadra  Freescale Semiconductor Inc., Austin, TX, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Transaction-level modeling is an essential component of system-level design. This paper advocates using rendezvous, a construct common to concurrent programming languages, as a theoretical foundation for transactions. Compared to regular function calls, rendezvous are atomic and support multipartiness and parallel composition. However, scheduling multiparty rendezvous is a challenging task due to its NP-hard complexity. This paper describes a heuristic algorithm that significantly reduces the scheduling complexity in practice. It first constructs a relationship graph among rendezvous. It then simplifies the graph and translates it into a decision tree, which assists the scheduler in partitioning and pruning the search space. Our experimental results show that the algorithm is able to improve the efficiency of the scheduler significantly.


REFERENCES

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1
IEEE INC. IEEE Standard SystemC Language Reference Manual (1666--2005). New York, NY 10016--5997, USA, 2005.
 
2
ISO/IEC(8652:1995). Ada Reference Manual -- Language and Standard Libraries. 1995.
 
3
Barrett, Geoff. occam3 reference manual. INMOS Ltd., 1992.
 
4
 
5
 
6
 
7
CELOXICA LTD. Handel-C Language Reference Manual. 2005.
 
8
Edwards, Stephen A and Tardieu, Olivier. SHIM: A Deterministic Model for Heterogeneous Embedded Systems. IEEE Transactions on Very Large Scale Integration Systems, 14, 8 (August 2006), 854--867.
 
9
Handshake Solutions, Haste Progamming Language Manual, 2008.
10
 
11
Nikhil, Rishiyur. Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions. In Philippe Coussy, Adam Morawiec, ed., High-Level Synthesis -- From Algorithm to Digital Circuit. Springer, 2008.
 
12
 
13

Collaborative Colleagues:
Di Wang: colleagues
Vyas Venkataraman: colleagues
Zhen Wang: colleagues
Wei Qin: colleagues
Hangsheng Wang: colleagues
Mrinal Bose: colleagues
Jayanta Bhadra: colleagues