NBTI-aware sleep transistor design for reliable power-gating

ABSTRACT

Negative Bias Temperature Instability (NBTI) has been regarded as most important source of reliability of CMOS devices, and specifically pMOS transistors.

In this work we focus on the NBTI-induced degradation of sleep transistor cells More in details we present a practical SPICE-based analysis framework for evaluating delay degradation of power-gated circuits due to NBTI-induced current capability reducing of pMOS sleep transistor. We also describe three NBTI-tolerant pMOS sleep transistor cell design approaches, in which the V<_i>th</i> increase due to NBTI is compensated through (i) sleep-transistor over-sizing, (ii) forward-body-biasing, (iii) equivalent 0-probability reduction of the sleep-transistor driving signal.

Characterization results on a commercial 45nm CMOS technology define fundamental guide-lines to be used during NBTI-aware sleep-transistor design, while experiments on an industrial benchmark highlight the importance of considering NBTI effect on pMOS sleep transistor design, emphasizing the effectiveness of the proposed design methodologies: <i>more than 85% of time-life extension.</i>

REFERENCES

• 1: N. Kimizuka, et.al. "Impact of bias temperature instability for direct tunneling ultra-thin gate oxide on MOSFET scaling," Symposium on VLSI Technology, 1999, pp. 73--74.
• 2: G. Chen, et.al. "Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Letters, Vol. 23, No. 12, pp. 734--736, Dec. 2002.
• 3: B.C. Paul, et.al. "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits," IEEE Electron Device Letters, Vol. 26, No. 8, Aug. 2005
• 4: S. Bhardwaj, et.al. "Predictive modeling of the NBTI effect for reliable design," CICC'06, pp. 9.3.1.--9.3.4.
• 5: Rakesh Vattikonda , Wenping Wang , Yu Cao, Modeling and minimization of PMOS NBTI effect for robust nanometer design, Proceedings of the 43rd annual Design Automation Conference, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1147172]
• 6: M. Alam, "Reliability- and process-variation aware design of integrated circuits,"Microelectronics Reliability, 48, pp. 1114--1122, Aug. 2008
• 7: Sanjay V. Kumar , Chris H. Kim , Sachin S. Sapatnekar, An analytical model for negative bias temperature instability, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233601]
• 8: Wenping Wang , Shengqi Yang , Sarvesh Bhardwaj , Rakesh Vattikonda , Sarma Vrudhula , Frank Liu , Yu Cao, The impact of NBTI on the performance of combinational and sequential circuits, Proceedings of the 44th annual Design Automation Conference, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278573]
• 9: Wenping Wang , Shengqi Yang , Yu Cao, Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect, Proceedings of the 9th international symposium on Quality Electronic Design, p.763-768, March 17-19, 2008
• 10: M. Anis, et.al. "Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits," IEEE Trans. on Computer-Aided Design, Vol. 22, No. 10, pp. 1324--1342, Oct. 2003.
• 11: Changbo Long , Lei He, Distributed sleep transistor network for power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.937-946, September 2004 [doi>10.1109/TVLSI.2004.832939]
• 12: Ashoka Sathanur , Antonio Pullini , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Timing-driven row-based power gating, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA [doi>10.1145/1283780.1283803]
• 13: Michael Keating , David Flynn , Rob Aitken , Alan Gibbons , Kaijian Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer Publishing Company, Incorporated, 2007
• 14: E. Pakbaznia, et.al. "Charge Recycling in Power-Gated CMOS Circuits," IEEE Trans. on CAD, Vol. 27, No. 10, pp. 1798--1811, Oct. 2008.
• 15: Andrea Calimera , Antonio Pullini , Ashoka Visweswara Sathanur , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology, Proceedings of the 17th ACM Great Lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy [doi>10.1145/1228784.1228903]
• 16: A. Sathanur, et.al. "Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing," DATE'07, pp. 1--6, Apr. 2007.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design

Keywords:
nbti, reliability, sizing, sleep-transistor