Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO

ABSTRACT

In this paper, we present the design of a P4 (Power-Performance-Process-Parasitic) aware voltage controlled oscillator (VCO) at nano-CMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a traditional Monte Carlo (TMC) method. A performance optimization of the VCO along with dual-oxide power minimization technique has been carried out in the presence of worst case process. The end product of the proposed methodology is a process aware, performance optimized, dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1% degradation in center frequency compared to target frequency, in the presence of <i>worst-case process</i> and parasitics. The dual-oxide physical design of the VCO is carried out at 90nm. To the best of the authors' knowledge, this is the first research reporting a dual-oxide nano-CMOS VCO design simultaneously optimized for power (including leakage), performance, parasitics and process.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design

Keywords:
dual oxide technology, nano-cmos, parasitics, performance aware design, power aware design, process variation, vco