Dual-threshold pass-transistor logic design

ABSTRACT

This paper introduces pass-transistor logic design with dual-threshold voltages. A set of single-rail, fully restored, pass-transistor gates are presented. Logic transistors are implemented with low threshold voltages and signal restoration transistors with high threshold voltages. Simulation is used to characterize the leakage power consumption, switching energy, and propagation delay of the proposed gates. A method to reduce circuit power by selectively replacing CMOS gates with the proposed gates is discussed and applied to the ISCAS'85 benchmark circuits. Relative to circuits composed entirely of conventional CMOS gates, use of the proposed SDPL gates achieves up to 49% reduction in leakage power and up to 63% reduction in total power consumption.

REFERENCES

• 1: ITRS (2007). http://www.itrs.net.
• 2: Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th annual Design Automation Conference, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514042]
• 3: R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079--1090, Jul. 1997.
• 4: K. Yano et al., "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 792--803, Jun. 1996.
• 5: M. Anis, M. Allam, and M. Elmasry, "Impact of technology scaling on CMOS logic styles," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 8, pp. 577--588, Aug. 2002.
• 6: G. Merrett and B. M. Al-Hashimi, "Leakage power analysis and comparison of deep submicron logic gates," in Proc. 14th Int. Workshop on Power, Timing, Modeling, Optimization, and Simulation (PATMOS), Sep. 2004, pp. 198--207.
• 7: A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473--484, Apr. 1992.
• 8: H. Al-Hertani, D. Al-Khalili, and C. Rozon, "Leakage power dissipation in UDSM logic gates," in Proc. 3rd IASTED Int. Conference on Circuits, Signals, and Systems, Oct. 2005.
• 9: E. Zitzler and L. Thiele, "Multiobjective evolutionary algorithms: a comparative case study and the strength pareto approach," IEEE Trans. Evolutionary Computation, vol. 3, no. 4, pp. 257--271, Nov 1999.
• 10: E. Zitzler, M. Laumanns, and L. Thiele, "Spea2: Improving the strength pareto evolutionary algorithm," in TIK-Report No. 103, Zurich, Switzerland: Swiss Federal Institute of Technology, 2001.
• 11: Q. Wang and S. B. K. Vrudhula, "Algorithms for minimizing standby power in deep submicrometer, dual-vt CMOS circuits," TCAD, vol. 21, no. 3, pp. 306--318, March 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Design

Keywords:
dual threshold, leakage, low power, pass transistor