High-performance, cost-effective heterogeneous 3D FPGA architectures

ABSTRACT

In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a novel design partitioning methodology that maps the heterogeneous computational resources of an FPGA into a number of die such that the total die area is minimized and the FPGA performance is maximized. Minimizing the total die area leads to direct manufacturing cost savings which is an important incentive to bring 3D technology to the fab and onto the market. An estimation framework is developed to assess the impact of silicon area utilized by 3D interconnect resources while taking into account the large area occupied by TSVs which is crucial to total die area of 3D FPGAs. In order to improve area and performance of 3D FPGAs, we design a novel 3D switch box with bypass TSVs. We also analyze the impact of different partitioning strategies on die area and find the optimal number of die that gives the largest reductions in total die area while maximizing the performance. Using a well-developed simulation infrastructure, we show that our methodologies can achieve an average reduction of 27.7% in total die area with a reduced interconnect path delay of about 58%.

REFERENCES

• 1: K. Banerjee, et. al., 3-D ICs: A Novel Chip Design for Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," Proc. of the IEEE, vol. 89(5), pp. 602--633, 2001.
• 2: A. W. Topol , D. C. La Tulipe, Jr. , L. Shi , D. J. Frank , K. Bernstein , S. E. Steen , A. Kumar , G. U. Singco , A. M. Young , K. W. Guarini , M. Ieong, Three-dimensional integrated circuits, IBM Journal of Research and Development, v.50 n.4/5, p.491-506, July 2006
• 3: M. Alexander, et. al., "Three-dimensional field-programmable gate arrays, ASIC Conference and Exhibit, 1995., Proc. of the Eighth Annual IEEE International, pp. 253--256, Sep 1995.
• 4: Waleed M. Meleis , Miriam Leeser , Paul Zavracky , Mankuan M. Vai, Architectural Design of a Three Dimensional FPGA, Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), p.256, September 15-16, 1997
• 5: Gaetano Borriello , Carl Ebeling , Scott A. Hauck , Steven Burns, The triptych FPGA architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.491-501, Dec. 1995 [doi>10.1109/92.475968]
• 6: Mingjie Lin , Abbas El Gamal , Yi-Chang Lu , Simon Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA [doi>10.1145/1117201.1117219]
• 7: A. J. Alexander, et. al., Placement and routing for three-dimensional FPGAs, in Fourth Canadian Workshop on Field-Programmable Devices, 1996, pp. 11--18.
• 8: Arifur Rahman , Shamik Das , Anantha P. Chandrakasan , Rafael Reif, Wiring requirement and three-dimensional integration technology for field programmable gate arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.44-54, February 2003 [doi>10.1109/TVLSI.2003.810003]
• 9: C. Ababei, et. al., "Three-dimensional place and route for FPGAs, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, no. 6, pp. 1132--1140, June 2006.
• 10: Young-Su Kwon , Payam Lajevardi , Anantha P. Chandrakasan , Frank Honoré , Donald E. Troxel, A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool, Proceedings of the 2005 international workshop on System level interconnect prediction, April 02-03, 2005, San Francisco, California, USA [doi>10.1145/1053355.1053371]
• 11: Mingjie Lin , Abbas El Gamal, A routing fabric for monolithically stacked 3D-FPGA, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA [doi>10.1145/1216919.1216921]
• 12: Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
• 13: Vasilis F. Pavlidis , Eby G. Friedman, Three-dimensional Integrated Circuit Design, Morgan Kaufmann Publishers Inc., San Francisco, CA, 2008
• 14: S. Wilton and N. Jouppi, "Cacti: an enhanced cache access and cycle time model," Solid-State Circuits, IEEE Journal of, vol. 31, no. 5, pp. 677--688, May 1996.
• 15: Cacti 5.3, Online, available at: http://quid.hpl.hp.com:9081/cacti/index.y?new.
• 16: Altera stratix ii device handbook, volume 1," http://www.altera.com/literature/hb/stx2/stratix2_handbook.pdf.
• 17: B. S. Landman , R. L. Russo, On a Pin Versus Block Relationship For Partitions of Logic Graphs, IEEE Transactions on Computers, v.20 n.12, p.1469-1479, December 1971 [doi>10.1109/T-C.1971.223159]
• 18: Payman Zarkesh-Ha , Jeffrey A. Davis , James D. Meindl, Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.6, p.649-659, Dec. 2000 [doi>10.1109/92.902259]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

General Terms:
Economics, Performance

Keywords:
3D integrated circuits, heterogeneous FPGA design