Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems

ABSTRACT

Three-dimensional (3D) integration of a single high performance microprocessor die and multiple DRAM dies has been considered as a viable option to tackle the looming memory wall problem. Meanwhile, on-chip decoupling capacitors are becoming increasingly important to ensure power delivery integrity, particularly for high-performance integrated circuits. Targeting at 3D processor-DRAM integrated computing systems, this paper proposes to use 3D stacked DRAM dies to provide decoupling capacitors for the processor die. This can well leverage the superior capacitor fabrication ability of DRAM to eliminate the area penalty of decoupling capacitor insertion on the processor die. For its practical implementation, a simple uniform decoupling capacitor network design strategy is presented, and circuit SPICE simulations and computer system simulations are carried out to quantitatively demonstrate the effectiveness and illustrate various design trade-offs.

REFERENCES

• 1: J.-Q. Lu, K. Rose, and S. Vitkavage, "3D Integration: Why, What, Who, When?," Future Fab International (http://www.future-fab.com/), pp. 25--27, July 2007.
• 2: R.S. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proceedings of the IEEE, vol. 94, pp. 1214--1224, June 2006.
• 3: Wm. A. Wulf , Sally A. McKee, Hitting the memory wall: implications of the obvious, ACM SIGARCH Computer Architecture News, v.23 n.1, p.20-24, March 1995 [doi>10.1145/216585.216588]
• 4: Christianto C. Liu , Ilya Ganusov , Martin Burtscher , Sandip Tiwari, Bridging the Processor-Memory Performance Gapwith 3D IC Technology, IEEE Design & Test, v.22 n.6, p.556-564, November 2005 [doi>10.1109/MDT.2005.134]
• 5: Taeho Kgil , Shaun D'Souza , Ali Saidi , Nathan Binkert , Ronald Dreslinski , Trevor Mudge , Steven Reinhardt , Krisztian Flautner, PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor, Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, October 21-25, 2006, San Jose, California, USA
• 6: Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb, Die Stacking (3D) Microarchitecture, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.469-479, December 09-13, 2006 [doi>10.1109/MICRO.2006.18]
• 7: Gabriel H. Loh , Yuan Xie , Bryan Black, Processor Design in 3D Die-Stacking Technologies, IEEE Micro, v.27 n.3, p.31-48, May 2007 [doi>10.1109/MM.2007.59]
• 8: Gabriel H. Loh, 3D-Stacked Memory Architectures for Multi-core Processors, Proceedings of the 35th International Symposium on Computer Architecture, p.453-464, June 21-25, 2008
• 9: Zhu, Power Distribution Network Design for VLSI, John Wiley & Sons, 2004
• 10: M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2007.
• 11: CACTI: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model, http://www.hpl.hp.com/research/cacti/.
• 12: M5: A modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture, http://www.m5sim.org/.
• 13: T.A.C.M. Claasen, "An Industry Perspective on Current and Future State of the Art in System-on-Chip (SoC) Technology," Proceedings of the IEEE, vol. 94, pp. 1121--1137, June 2006.
• 14: J.-Q. Lu, T.S. Cale, and R.J. Gutmann, "Wafer-level three-dimensional hyper-integration technology using dielectric adhesive wafer bonding," Materials for Information Technology: Devices, Interconnects and Packaging (Eds. E. Zschech, C. Whelan, T. Mikolajick), pp. 386--397, Springer-Verlag (London) Ltd, August 2005.
• 15: K. Itoh, VLSI Memory Chip Design, Springer, 2001.
• 16: G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, "Power delivery for 3d chip stacks: Physical modeling and design implication," in Electrical Performance of Electronic Packaging, 2007 IEEE, Atlanta, GA, Oct. 2007, pp. 205--208.
• 17: Mikhail Popovich , Michael Sotman , Avinoam Kolodny , Eby G. Friedman, Effective radii of on-chip decoupling capacitors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.894-907, July 2008 [doi>10.1109/TVLSI.2008.2000454]
• 18: Semiconductor Industry Association, The International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net/reports.html.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

General Terms:
Design

Keywords:
decoupling capacitor, dram, three-dimentional integration