Process variation mitigation via post silicon clock tuning

ABSTRACT

Manufacturing process corner, voltage and temperature (PVT) conditions lead to variation in path delays and clock skews. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. These buffers are tuned to maximize operating clock frequency of a design. In this paper, we report a study on using measured delays on selected patterns to determine which buffers should be targeted for tuning. Based on statistical simulation studies, it is found that the proposed approach can improve clock frequency by as much as 9% in the average case.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Measurement, Performance

Keywords:
performance, post-silicon tuning, process variation