Glitch-free design for multi-threshold CMOS NCL circuits

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Glitch-free design for multi-threshold CMOS NCL circuits

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

SESSION: VLSI circuits table of contents

Pages 215-220

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Ahmad Al Zahrani	University of Arkansas, Fayetteville, AR, USA
Andrew Bailey	University of Arkansas, Fayetteville, AR, USA
Guoyuan Fu	University of Arkansas, Fayetteville, AR, USA
Jia Di	University of Arkansas, Fayetteville, AR, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 21, Downloads (12 Months): 50, Citation Count: 0

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ABSTRACT

In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into asynchronous NULL Convention Logic (NCL) circuits. A one-stage 8x8 NCL array multiplier is designed using the proposed method and compared with the previously published paradigm. Evaluation results of glitches, throughput, and power efficiency have shown advantages of the proposed design in all these categories over the state-of-the-art. The effect of supply voltage scaling on the proposed design is also examined and presented.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Mutoh et. al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits, Aug 1995, pp. 847--854.
	2	J. Kao and A. P. Chandrakasan, Dual-Threshold Voltage Techniques for Low-Power Digital Circuits," IEEE Journal of Solid-State Circuits, Vol. 35, NO. 7, July 2000.
	3	J. Kao and A. Chandrakasan, "MTCMOS sequential circuits, European Solid-State Circuits Conference, 2001, pp. 332--339.
	4	Steve Masteller, Lief Sorenson, "Cycle Decomposition in NCL, IEEE Design and Test of Computers, vol. 20, no. 6, pp. 38--43, Nov/Dec, 2003
	5	A. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, "Ultra-Low Power Delay-Insensitive Circuit Design, 2008 IEEE Midwest Symposium on Circuits and Systems, Aug. 2008.
	6	A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. Smith, Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power, accepted for publication by Journal of Low Power Electronics, Vol. 4, NO. 3, December 2008.
	7	Alex Kondratyev , Kelvin Lwin, Design of Asynchronous Circuits Using Synchronous CAD Tools, IEEE Design & Test, v.19 n.4, p.107-117, July 2002 [doi>10.1109/MDT.2002.1018139]
	8	Speedup of Self-Timed Digital Systems Using Early Completion, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, p.107, April 25-26, 2002