STI stress aware placement optimization based on geometric programming

ABSTRACT

Shallow trench isolation(STI) is the mainstream CMOS isolation technology for advanced integrated circuits. While STI process gives the isolation benefits due to its scalable characteristics, exploiting the compressive stress exerted by STI wells on device active regions to improve performance of devices has been one of the major industry focuses. However, in the present research of VLSI physical design, there has no yet a global optimization methodology on the whole chip layout to control the size of the STI wells, which affects the stress magnitude along with the size of active region of transistors. In this paper, we present a novel methodology that is capable of determining globally the optimal STI well width following the chip placement stage. The methodology is based on the observation that both of the terms in charge of chip width minimization and transistor channel mobility optimization in the objective function can be modeled as posynomials of the design variables, that is, the width of STI wells. Then, this stress aware placement optimization problem could be solved efficiently as a convex geometric programming (GP) problem. Finally, by a MOSEK GP problem solver, we do our STI width aware placement optimization on the given placements of some GSRC and IBM-PLACE benchmarks. Experiment results demonstrated that our methodology can obtain decent results with an acceptable runtime when satisfy the necessary location constraints from DRC specifications.

REFERENCES

• 1: N. Shah et al., "Stress Modeling of Nanoscale", Master thesis, University of Florida, USA, 2005.
• 2: S.E. Thompson et al., "A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1um2 SRAM Cell", Proceedings of International Electron Device Meeting,pp. 61--64, 2002.
• 3: S.E. Thompson et al., "A Logic Nanotechnology Featuring Strained-Silicon", IEEE Electron Device Letters, vol. 25, no. 4, pp. 191--193, April 4, 2004.
• 4: F. Andrieu et al., "Experimental and Comparative Investigation of Low and High Field Transport in Substrate- and Process- Induced Strained Nanoscale MOSFETs", Proceedings of Symposium on VLSI Technology, pp. 176--177, 2005.
• 5: K. Mistry et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology", Proceedings of Symposium on VLSI Technology, pp. 50--51, 2005.
• 6: Vivek Joshi , Brian Cline , Dennis Sylvester , David Blaauw , Kanak Agarwal, Stress aware layout optimization, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA [doi>10.1145/1353629.1353666]
• 7: V. Moroz et al., "The Impact of Layout on Stress-Enhanced Transistor Performance", Proceedings of International Conference on Simulation of Semiconductor Processes and Devices, pp. 143--146, 2005.
• 8: M.V. Dunga et al., "Holistic Model for Mobility Enhancement Through Process-Induced Stress", Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits, pp. 43--46, 2005.
• 9: H. Tsuno et al., "Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation", Proceedings of Symposium on VLSI Technology, pp. 204--205, 2007.
• 10: Andrew B. Kahng , Puneet Sharma , Rasit O. Topaloglu, Exploiting STI stress for performance, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 11: A. Dag et al., "Performing STI process control using large-spot-size Fourier-transform reflectometry", www.micromagazine.com, April 2003.
• 12: S.P. Boyd et al., "A Tutorial on Geometric Programming", Optimization and Engineering, Springer Netherlands, vol. 8, no. 1, pp. 67--127, 2007.
• 13: Xiaoping Tang , Xin Yuan , Michael S. Gray, Practical method for obtaining a feasible integer solution in hierarchical layout optimization, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 14: http://vlsicad.ucsd.edu/GSRC.
• 15: http://er.cs.ucla.edu/benchmarks/ibm-place.
• 16: http://www.mosek.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Performance

Keywords:
placement optimization, sti stress, sti well width