Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature

ABSTRACT

We have introduced the concept of the Moebius strip into LSI circuit design, realizing 8.4 FO4-Inverter throughput for any kind of digital logic circuit. The Moebius circuit operates in a logic gate level pipeline, and has error detection and error gate search features, using a self-timed architecture.

REFERENCES

• 1: M. Ikeda, et al. Lags system using data/instruction grain power control. ISSCC Dig. Tech. Papers, pages 66--67, February 2007.
• 2: Burleson W.P., Ciesielski M., Klass F., Liu W. Wave-pipelining: a tutorial and research survey. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 6:464--474, September 1998.
• 3: Jing-ling Yang , Chiu-sing Choy , Cheong-fat Chan , Kong-pong Pun, Design for Self-Checking and Self-Timed Datapath, Proceedings of the 21st IEEE VLSI Test Symposium, p.417, April 27-May 01, 2003

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Performance, Reliability

Keywords:
dcvsl, error detect, high speed digital, pipeline, soft error