Study of leakage current mechanisms in ballistic deflection transistors

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Study of leakage current mechanisms in ballistic deflection transistors

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

POSTER SESSION: Poster session 1 table of contents

Pages 165-168

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Vikas Kaushal	University of Massachusetts Lowell, Lowell, MA, USA
Quentin Diduck	University of Massachusetts Lowell, Lowell, MA, USA
Martin Margala	University of Massachusetts Lowell, Lowell, MA, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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ABSTRACT

In this paper, the Ballistic Deflection Transistor (BDT) is reviewed for variations in performance of the device including leakage with respect to geometry modifications. Monte Carlo and Silvaco modeling tools are used to study current leakage mechanism in BDT. Low power selection criteria and theory behind position of deflector in the device are examined. Since ballistic conduction is not dissipative, power loss should be low. Leakage can be reduced by placing deflector at about 25% of its own length lower than the exact centre of the device. Current leakages that occurred during device operation are compared with each other and with the output current. It is observed that magnitude of leakage current is distinct at different ports of the device. For a specific set of parameters, leakage is comparable to the output which essentially motivates to choose optimum device architecture.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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