A process variation tolerant self-compensating FinFET based sense amplifier design

ABSTRACT

With the emerging nanoscale devices, SIA roadmap identifies FinFET as a candidate for post-planar end-of-roadmap CMOS device. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET in ITRS. Yield loss due to device and process variation has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variation in sense amplifiers lead to significant loss of yield. In this paper, we present a FinFET based Process Variation Tolerant Sense Amplifier design, that exploits the backgate of FinFET devices for dynamic compensation against process variation. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without significant process variations.

REFERENCES

• 1: http://www.itrs.net/reports.html
• 2: Chenming Hu et al, FinFET-A Self-Aligned Double-Gate MOSFET," Trans. IEEE Electron Devices, Dec 2000.
• 3: Ying Zhang Wong et, al, "Fabrication of metal gated FinFETs through complete gate silicidation with Ni. Electron Devices, IEEE Transactions on Volume 51, Issue 12, Dec. 2004.
• 4: Feng Wang , Yuan Xie , Kerry Bernstein , Yan Luo, Dependability Analysis of Nano-scale FinFET circuits, Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, p.399, March 02-03, 2006 [doi>10.1109/ISVLSI.2006.35]
• 5: Bin Yu et al, FinFET Scaling to 10nm Gate Length in Electron Devices Meeting 2002 IEDM '02. Digest. International.
• 6: D. M. Fried et. al, "Scaling Beyond the 65 nm Node with FinFET-DGCMOS, in IEEE Custom Integrated Circuits Conference 2003.
• 7: Tarun Sairam , Wei Zhao , Yu Cao, Optimizing finfet technology for high-speed and low-power design, Proceedings of the 17th ACM Great Lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy [doi>10.1145/1228784.1228807]
• 8: Rajiv V. Joshi, et al, FinFET SRAM for High-Performance Low-Power Applications" in IEEE 2004.
• 9: Rajiv V. Joshi , Keunwoo Kim , Richard Q. Williams , Edward J. Nowak , Ching-Te Chuang, A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology, Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems, p.665-672, January 06-10, 2007 [doi>10.1109/VLSID.2007.182]
• 10: Ching-Te Chuang et al, Novel high-density low-power logic circuit techniques using DG devices" Electron Devices, IEEE Transactions on Volume 52, Issue 10, Oct. 2005 Page(s):2339 -- 2342
• 11: Kaushik Roy et al, "FinFET SRAM- Device and circuit and Design Considerations in IEEE 2004
• 12: http://www.eas.asu.edu/~ptm/
• 13: Aiyappan Natarajan , Vijay Shankar , Atul Maheshwari , Wayne Burleson, Sensing Design Issues in Deep Submicron CMOS SRAMs, Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design, p.42-45, May 11-12, 2005 [doi>10.1109/ISVLSI.2005.67]
• 14: B. Wicht et al., Yield and speed optimization of a latch type voltage sense amplifier, IEEE J. Solid-State Circuits, Jul. 2004.
• 15: Saibal Mukhopadhyay , Arijit Raychowdhury , Hamid Mahmoodi , Kaushik Roy, Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM, Proceedings of the 14th Asian Test Symposium on Asian Test Symposium, p.176-181, December 18-21, 2005 [doi>10.1109/ATS.2005.73]
• 16: Steevan Rodriques, M.S Bhat, "Impact of Process Induced Transistor Matched on Sense Amplifier, ADCOM 2006
• 17: J. Yeung, Hamid Mahmoodi Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies, IEEE International SOC Conference, 2006
• 18: Kaushik Roy et al, Process variation in embedded memories:failiure analysis and variation aware architecture Proc. IEEE 2005.
• 19: Hspice http://www.synopsys.com

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

General Terms:
Design, Measurement, Performance

Keywords:
finfet, process -variation, robustness, sense amplifier, sram, yield