BISM: built-in self map for hybrid crossbar nano-architectures

ABSTRACT

In hybrid nano architectures, self-assembled nanoscale crossbars are fabricated on top a reliable CMOS subsystem. Bottom-up selfassembly process used in the fabrication of nanoscale devices yields significantly more defects compared to the conventional top-down lithography used in CMOS fabrication. Therefore, applying defect tolerant design schemes is inevitable in order to map the design to these programmable fabrics by bypassing defects. In this paper, we present an alternative approach for defect tolerant mapping in which the mapping phase is built into the programmable fabric and reliable on-chip resources are used for on-the-fly defectfree mapping. This built-in self map (BISM) scheme significantly reduces the complexity of defect tolerance during design time as well as post-fabrication configuration time. Various BISMschemes are presented and their efficiencies in terms of defect tolerance and mapping time are compared.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Reliability

Keywords:
crossbar array, emerging nanotechnologies, logic mapping