| Central vs. distributed dynamic thermal management for multi-core processors: which one is better? |
| Full text |
Pdf
(566 KB)
|
Source
|
Great Lakes Symposium on VLSI
archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI
table of contents
Boston Area, MA, USA
POSTER SESSION: Poster session 1
table of contents
Pages: 137-140
Year of Publication: 2009
ISBN:978-1-60558-522-2
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 11, Downloads (12 Months): 81, Citation Count: 0
|
|
|
ABSTRACT
In this paper we investigate and contrast two techniques to maximize the performance of multi-core processors under thermal constraints. The first technique is a distributed dynamic thermal management system that maximizes the total performance without exceeding given thermal constraints. In our scheme, each core adjusts its operating parameters, i.e., frequency and voltage, according to its temperature which is measured using integrated thermal sensors. We propose a novel controller that dynamically adapts the system to simultaneously avoid timing errors and thermal violations. For comparison purposes, we implement a second technique based on a runtime centralized, optimal system that uses combinatorial optimization techniques to calculate the optimal frequencies and voltages for the different cores to maximize the total throughput under thermal constraints. To empirically validate our techniques, we put together an extensive tool chain that incorporates thermal and power consumption simulators to characterize the performance of multi-core processors for a number of configurations ranging from 2 cores at 90 nm to 16 cores at 32 nm. Our results show that both investigated techniques are capable of delivering significant improvements (about 40% for 16 cores) over standard frequency and voltage planning techniques. From the results, we outline the main advantages and disadvantages of both techniques.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
|
| |
2
|
D. C. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0, Tech. Rep. CS-TR-1997-1342, 1997. {Online}. Available: citeseer.ist.psu.edu/burger97simplescalar.html
|
 |
3
|
|
| |
4
|
M. Kadin and S. Reda, Frequency and Voltage Planning for Multi-Core Processors Under Thermal Constraints," in International Conference on Computer Design, 2008, pp. 463--470.
|
 |
5
|
|
| |
6
|
W. Liao, L. He, and K. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level, Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24(7), pp. 1042--1053, 2005.
|
| |
7
|
K. Skadron, S. Ghosh, S. Velusamy, K. Sankaranarayanan, and M. Stan, "HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design," Transactions on VLSI Systems, vol. 15(5), pp. 501--513, 2006.
|
| |
8
|
|
| |
9
|
S. Wilton and N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal Solid-State Circuits, vol. 31(5), pp. 677--688, 1996.
|
|