Definition and application of approximate necessary assignments

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Definition and application of approximate necessary assignments

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

POSTER SESSION: Poster session 1 table of contents

Pages 105-108

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Irith Pomeranz	Purdue University, West Lafayette, IN, USA
Sudhakar M. Reddy	University of Iowa, Iowa City, IA, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 0

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ABSTRACT

A necessary assignment for a fault f is a line value that must be assigned by a test vector that detects f. A higher number of necessary assignments translates into a lower test generation effort since the test generation process has a larger number of values that it must assign, and therefore, fewer options that it can explore. To increase the number of available necessary assignments, we define approximate necessary assignments as line values that are assigned by most of the test vectors for a fault. We describe a heuristic procedure for computing approximate necessary assignments for inputs and demonstrate their effectiveness in reducing the test generation effort of a random test generation process.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1995.
	2	P. Goel and B. C. Rosales, "Test Generation and Dynamic Compaction of Tests", in Proc. Test Conf., 1979, pp. 189--192.
	3	Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy, COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.194-203, October 26-30, 1991
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	6	S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Dec. 1995, pp. 1496--1504.
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