Soft error rate computation in early design stages using boolean satisfiability

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Soft error rate computation in early design stages using boolean satisfiability

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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents

Boston Area, MA, USA

POSTER SESSION: Poster session 1 table of contents

Pages 101-104

Year of Publication: 2009

ISBN:978-1-60558-522-2

Authors

Syed Z. Shazli	Northeastern University, Boston, MA, USA
Mehdi B. Tahoori	Northeastern University, Boston, MA, USA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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ABSTRACT

Soft errors, due to cosmic radiations, are the major reliability barriers for VLSI designs. To meet reliability constraints in a costeffective way, it is critical to assess soft error reliability parameters in early design stages. In this paper, we present a framework to accurately obtain soft error rate (SER) for high-level (behavioral) descriptions (Verilog or VHDL). We transform the SER problem into an equivalent Boolean satisfiability (SAT) problem and use state-of-the-art SAT-solvers to obtain SER. We have developed an automated flow to convert high-level hardware descriptions into SAT formulations for exact SER computation. We compare our technique to traditional fault simulation techniques. The experimental results show that fault simulations with orders of magnitude run time overhead still result in significantly inaccurate underestimation of SER values. We applied the technique on the largest ISCAS benchmark circuits and found out that it scales well.

REFERENCES

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