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Voltage-island driven floorplanning considering level-shifter positions
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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents
Boston Area, MA, USA
SESSION: Low power table of contents
Pages 51-56  
Year of Publication: 2009
ISBN:978-1-60558-522-2
Authors
Bei Yu  Tsinghua University, Beijing, China
Sheqin Dong  Tsinghua University, Beijing, China
Satoshi Goto  Waseda University, Kitakyushu, Japan
Song Chen  Waseda University, Kitakyushu, Japan
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M.Hamada and T.Kuroda. Utilizing surplus timing for power reduction. CICC, pages 89--92, 2001.
 
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Xianlong Hong, Sheqin Dong. Non-slicing foorplan and placement using corner block list topological representation. IEEE Transaction on CAS, 51:228--233, 2004.

Collaborative Colleagues:
Bei Yu: colleagues
Sheqin Dong: colleagues
Satoshi Goto: colleagues
Song Chen: colleagues