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VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power
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Great Lakes Symposium on VLSI archive
Proceedings of the 19th ACM Great Lakes symposium on VLSI table of contents
Boston Area, MA, USA
SESSION: Low power table of contents
Pages 39-44  
Year of Publication: 2009
ISBN:978-1-60558-522-2
Authors
Wan-Yu Lee  National Chiao Tung University, Hsinchu, Taiwan Roc
Iris Hui-Ru Jiang  National Chiao Tung University, Hsinchu, Taiwan Roc
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate the impact of process variability on throughput and power, voltage and frequency islands are introduced into chip-multiprocessors. Thus, voltage island frequency island chip-multiprocessors enable per-core scaling on the supply voltage and operating frequency. It can naturally collaborate with dynamic voltage frequency scaling. The process variations are characterized through an analytical model, and are quantified through Monte Carlo analysis. Compared with the design without process variations, when 70 threads are run on a chip of 70 small cores, our results show throughput degradation is 0.06%, while power reduction is 36.27%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Wan-Yu Lee: colleagues
Iris Hui-Ru Jiang: colleagues