Safe clocking for the setup and hold timing constraints in datapath synthesis

ABSTRACT

The setup and hold timing constraints are two types of timing constraints, which should be kept by each operation, and they may be violated by the timing variation of control signals. In this paper, we show that we can solve such potential timing violations in high-level synthesis without degrading speed performance, but by devising register assignment and clocking scheme. That is, we will combine Backward-Data-Direction (BDD) clocking, Forward-Data-Direction (FDD) clocking, and Structural Robustness against delay Variation (SRV)-based register assignment to solve potential timing violations. First, we formulate the problem as a minimum register assignment problem for datapaths which has a proper ordered clocking. After that, we propose an integer linear programming (ILP) formulation and show the experimental results for some benchmark circuits.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

General Terms:
Design

Keywords:
datapath synthesis, ordered clocking, register assignment