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ABSTRACT

We propose a novel flash memory management software for SLC/MLC combined flash memories which are recently introduced to provide flexible and cost-efficient embedded storage systems. To provide a fast and large capacity of flash memory, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page invokes a small migration cost. We also propose the bypassing technique which sends a large sequential data into the MLC flash directly not through the SLC log buffer. From the experiments, we can know that the proposed scheme utilizes the SLC log buffer effectively providing better performance compared with the previous flash management schemes for the SLC/MLC combined flash.¹

REFERENCES

• 1: T. Cho et al. "A dual-mode NAND flash memory: 1--Gb multilevel and high-performance 512-Mb single-level modes," IEEE Journal of Solid-State Circuits, Vol. 36, Issue 11, 2001.
• 2: Li-Pin Chang, Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
• 3: Samsung Electronics, 4Gb Flex-OneNAND M-die, http://www.samsung.com/global/business/semiconductor/products/fusionmemory/Products_FlexOneNAND.html.
• 4: Toshiba America Electronic Components, Inc., mobileLBA-NAND, http://www.toshiba.com/taec.
• 5: J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. "A space-efficient flash translation layer for compact flash systems," IEEE Transactions on Consumer Electronics, vol. 48, no. 2, pp. 366--375, 2002.
• 6: Sang-Won Lee , Dong-Joo Park , Tae-Sun Chung , Dong-Ho Lee , Sangwon Park , Ha-Joo Song, A log buffer-based flash translation layer using fully-associative sector translation, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.3, p.18-es, July 2007 [doi>10.1145/1275986.1275990]
• 7: S. Lee, D. Shin, and J. Kim. "LAST: locality-aware sector translation for NAND flash memory-based storage systems," Proc. of SPEED'08, Salt Lake City, Utah, Feb. 2008.
• 8: Jeong-Uk Kang , Heeseung Jo , Jin-Soo Kim , Joonwon Lee, A superblock-based flash translation layer for NAND flash memory, Proceedings of the 6th ACM & IEEE International conference on Embedded software, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176887.1176911]
• 9: Chanik Park , Wonmoon Cheon , Yangsup Lee , Myoung-Soo Jung , Wonhee Cho , Hanbin Yoon, A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications, Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping, p.202-208, May 28-30, 2007 [doi>10.1109/RSP.2007.8]
• 10: S. H. Park, J. W. Park, J. M. Jeong, J. H. Kim and S. D. Kim. "A mixed flash translation layer structure for SLC-MLC combined flash memory system," Proc. of SPEED'08, Salt Lake City, Utah, Feb. 2008.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  J. Computer Applications
  J.7 COMPUTERS IN OTHER SYSTEMS
      Subjects: Consumer products

General Terms:
Algorithms, Design

Keywords:
SLC/MLC combined flash, embedded system, flash memory, flash translation layer, storage system