CPS-SIM: configurable and accurate clock precision solid state drive simulator

ABSTRACT

NAND flash memory is the most widely used storage medium in embedded systems today due to its many advantages such as light weight, low power consumption, and shock resistance. Recently, solid state drives (SSDs), which use NAND flash memory to store data, are replacing conventional magnetic disks in laptops and some server computers. In the SSDs, to achieve both high performance and large capacity, a number of flash memory chips are connected to multiple buses and SSD firmware exploits parallel accesses by using interleaving and overlapping techniques. However, it is still unclear how many buses or chips should be used and how to drive those chips and buses to satisfy performance that may be required. To help answer these questions, we have developed a clock precision SSD simulator (CPS-SIM) that simulates the internal behavior of an SSD and that reports timing and utilization information. From the accurate timing and utilization results of CPS-SIM, we can discover the optimal hardware configuration including the number of buses and chips and their interconnections in an SSD. Also, it allows for fast development and verification of SSD firmware that runs an FTL (Flash Translation Layer) optimized for an SSD. Unlike FTLs for embedded flash memory, the FTL for an SSD must utilize the concurrency of the multiple chips and buses. By supporting concurrency, our CPS-SIM provides a flexible environment for design of SSD firmware that drives the multiple flash memory chips and also that schedules data transmissions via the multiple buses.

REFERENCES

• 1: "2G x 8Bit / 4G x 8 Bit / 8G x 8 Bit NAND Flash memory (K9WBG08U1M) Data Sheets," Samsung Electronics, Co, 2007.
• 2: Nitin Agrawal , Vijayan Prabhakaran , Ted Wobber , John D. Davis , Mark Manasse , Rina Panigrahy, Design tradeoffs for SSD performance, USENIX 2008 Annual Technical Conference on Annual Technical Conference, p.57-70, June 22-27, 2008, Boston, Massachusetts
• 3: Hyojun Kim , Seongjun Ahn, BPLRU: a buffer management scheme for improving random writes in flash storage, Proceedings of the 6th USENIX Conference on File and Storage Technologies, p.1-14, February 26-29, 2008, San Jose, California
• 4: Sang-Won Lee , Dong-Joo Park , Tae-Sun Chung , Dong-Ho Lee , Sangwon Park , Ha-Joo Song, A log buffer-based flash translation layer using fully-associative sector translation, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.3, p.18-es, July 2007 [doi>10.1145/1275986.1275990]
• 5: Jeong-Uk Kang , Heeseung Jo , Jin-Soo Kim , Joonwon Lee, A superblock-based flash translation layer for NAND flash memory, Proceedings of the 6th ACM & IEEE International conference on Embedded software, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176887.1176911]
• 6: Jongmin Lee , Sunghoon Kim , Hunki Kwon , Choulseung Hyun , Seongjun Ahn , Jongmoo Choi , Donghee Lee , Sam H. Noh, Block recycling schemes and their cost-based optimization in nand flash memory based storage system, Proceedings of the 7th ACM & IEEE international conference on Embedded software, September 30-October 03, 2007, Salzburg, Austria [doi>10.1145/1289927.1289956]
• 7: "YAFFS (Yet Another Flash File System) Specification Version 0.3," http://www.aleph1.co.uk/yaffs/, 2002.
• 8: D. Woodhouse, "JFFS: The Journaling Flash File System," in Proceedings of the Ottawa Linux Symposium 2001, 2001.
• 9: "Understanding the Flash Translation Layer (FTL) Specification," Intel Corporation, 1998.
• 10: J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, "A Space-efficient Flash Translation Layer for CompactFlash Systems," IEEE Transactions on Consumer Electronics, vol. 28, 2002.
• 11: Yi-Lin Tsai , Jen-Wei Hsieh , Tei-Wei Kuo, Configurable NAND Flash Translation Layer, Proceedings of the IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing -Vol 1 (SUTC'06), p.118-127, June 05-07, 2006 [doi>10.1109/SUTC.2006.46]
• 12: Mendel Rosenblum , John K. Ousterhout, The design and implementation of a log-structured file system, ACM Transactions on Computer Systems (TOCS), v.10 n.1, p.26-52, Feb. 1992 [doi>10.1145/146941.146943]
• 13: "Solid State Drive MSP-SATA7035 3.5-inch Product Specification," Mtron, Co., 2007.
• 14: Seon-yeong Park , Dawoon Jung , Jeong-uk Kang , Jin-soo Kim , Joonwon Lee, CFLRU: a replacement algorithm for flash memory, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176760.1176789]
• 15: Todd Dinkelman, "SSDs A Shift in Data Storage", Flash Memory Summit, 2008.

INDEX TERMS

Primary Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.8 Performance

Additional Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.2 Storage Management

General Terms:
Design, Experimentation, Performance

Keywords:
FTL (flash translation layer), NAND flash memory, SSD (solid state drive), clock precision SSD simulator, configurability