Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

ABSTRACT

The existing work on via allocation in 3D ICs ignores power/ground vias' ability to simultaneously reduce voltage bounce and remove heat. This article develops the first in-depth study on the allocation of power/ground vias in 3D ICs with simultaneous consideration of power and thermal integrity. By identifying principal ports and parameters, effective electrical and thermal macromodels are employed to provide dynamic power and thermal integrity as well as sensitivity with respect to via density. With the use of sensitivity, an efficient via allocation simultaneously driven by power and thermal integrity is developed. Experiments show that, compared to sequential power and thermal optimization using static integrity, sequential optimization using the dynamic integrity reduces nonsignal vias by up to 18%, and simultaneous optimization using dynamic integrity further reduces nonsignal vias by up to 45.5%.

REFERENCES

• 1: Charles J. Alpert , Andrew B. Kahng , So-Zen Yao, Spectral partitioning with multiple eigenvectors, Discrete Applied Mathematics, v.90 n.1-3, p.3-26, Jan. 15, 1999 [doi>10.1016/S0166-218X(98)00083-3]
• 2: Antoulas, A., Sorensen, D., and Gugercin, S. 2001. A survey of model reduction methods for large scale systems. Contemporary Math. 193--219.
• 3: Astrid, P., Weiland, S., and Willcox, K. 2007. Missing point estimation in models described by proper orthogonal decomposition. IEEE Trans. Autom. Control.
• 4: Banerjee, K., Souri, S. J., Kapur, P., and Saraswat, K. C. 2001. 3D ICs: A novel chip design for improving deep submicron interconnect performance and systems-on-chip integration. Proc. IEEE, 602--633.
• 5: George Edward Pelham Box , Gwilym M. Jenkins, Time Series Analysis: Forecasting and Control, Prentice Hall PTR, Upper Saddle River, NJ, 1994
• 6: Ting Yen Chiang , Kaustav Banerjee , Krishna C. Saraswat, Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 7: J. Cong , Jie Wei , Yan Zhang, A thermal-driven floorplanning algorithm for 3D ICs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.306-313, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382591]
• 8: J. Cong , Yan Zhang, Thermal via planning for 3-D ICs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.745-752, November 06-10, 2005, San Jose, CA
• 9: Das, S. 2004. Design automation and analysis of three dimentional integrated circuits Ph. D thesis, Massachusetts Institute of Technology.
• 10: W. Rhett Davis , John Wilson , Stephen Mick , Jian Xu , Hao Hua , Christopher Mineo , Ambarish M. Sule , Michael Steer , Paul D. Franzon, Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design & Test, v.22 n.6, p.498-510, November 2005 [doi>10.1109/MDT.2005.136]
• 11: Chris Ding , Hongyuan Zha, Spectral Clustering, Ordering and Ranking: Statistical Learning with Matrix Factorizations, Springer Publishing Company, Incorporated, 2008
• 12: Grimme, E. J. 1997. Krylov projection methods for model reduction Ph. D thesis, University of Illinois at Urbana-Champaign.
• 13: P. Feldmann , F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.88-92, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382548]
• 14: Brent Goplen , Sachin Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.86, November 09-13, 2003 [doi>10.1109/ICCAD.2003.60]
• 15: Brent Goplen , Sachin Sapatnekar, Thermal via placement in 3D ICs, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA [doi>10.1145/1055137.1055171]
• 16: Young-Seok Hong , Heeseok Lee , Joon-Ho Choi , Moon-Hyun Yoo , Jeong-Taek Kong, Analysis for Complex Power Distribution Networks Considering Densely Populated Vias, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.208-212, March 21-23, 2005 [doi>10.1109/ISQED.2005.19]
• 17: Ravi Kannan , Santosh Vempala , Adrian Vetta, On clusterings: Good, bad and spectral, Journal of the ACM (JACM), v.51 n.3, p.497-515, May 2004 [doi>10.1145/990308.990313]
• 18: J. U. Knickerbocker , P. S. Andry , L. P. Buchwalter , A. Deutsch , R. R. Horton , K. A. Jenkins , Y. H. Kwark , G. McVicker , C. S. Patel , R. J. Polastre , C. Schuster , A. Sharma , S. M. Sri-Jayantha , C. W. Surovic , C. K. Tsang , B. C. Webb , S. L. Wright , S. R. McKnight , E. J. Sprogis , B. Dang, Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM Journal of Research and Development, v.49 n.4/5, p.725-753, July 2005
• 19: Hang Li , Zhenyu Qi , Sheldon X.-D. Tan , Lifeng Wu , Yici Cai , Xianlong Hong, Partitioning-based approach to fast on-chip decap budgeting and minimization, Proceedings of the 42nd annual Design Automation Conference, June 13-17, 2005, Anaheim, California, USA [doi>10.1145/1065579.1065627]
• 20: Peng Li , L. T. Pileggi , M. Asheghi , R. Chandra, Efficient full-chip thermal modeling and analysis, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.319-326, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382594]
• 21: Peng Li , Weiping Shi, Model order reduction of linear networks with massive ports via frequency-dependent port packing, Proceedings of the 43rd annual Design Automation Conference, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146978]
• 22: Xin Li , Peng Li , L. T. Pileggi, Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.806-812, November 06-10, 2005, San Jose, CA
• 23: Zhuoyuan Li , Xianlong Hong , Qiang Zhou , Shan Zeng , Jinian Bian , Hannah Yang , Vijay Pitchumani , Chung-Kuan Cheng, Integrating dynamic thermal via planning with 3D floorplanning algorithm, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA [doi>10.1145/1123008.1123048]
• 24: Liao, W., He, L., and Lepak, K. 2005. Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 1042--1053.
• 25: Sung Kyu Lim, Physical Design for 3D System on Package, IEEE Design & Test, v.22 n.6, p.532-539, November 2005 [doi>10.1109/MDT.2005.149]
• 26: Pu Liu , S. X. -D. Tan , Hang Li , Zhenyu Qi , Jun Kong , B. McGaughy , Lei He, An efficient method for terminal reduction of interconnect circuits considering delay variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.821-826, November 06-10, 2005, San Jose, CA
• 27: Moore, B. 1981. Principal component analysis in linear systems: Controllability, observability, and model reduction. IEEE Trans. Autom. Control, 17--32.
• 28: Odabasioglu, A., Celik, M., and Pileggi, L. 1998. PRIMA: Passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst., 645--654.
• 29: Muruhan Rathinam , Linda R. Petzold, A New Look at Proper Orthogonal Decomposition, SIAM Journal on Numerical Analysis, v.41 n.5, p.1893-1925, 2003 [doi>10.1137/S0036142901389049]
• 30: Ruehli, A. E. 1974. Equivalent circuits models for three dimensional multiconductor systems. IEEE Trans. Microwave Theory Techniq. 216--220.
• 31: Ryu, C., Chung, D., Lee, J., Lee, K., Oh, J., et. al. 2005. High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3D chip stacking package. In Proceedings of the IEEE Conference on Electrical Performance of Electronic Packaging (EPEP).
• 32: Sapatnekar, S. 2006. Physical design automation challenges for 3D ICs. In International Conference on IC Design and Technology.
• 33: Su, H., K. Gala, and Sapatnekar, S. 2003. Analysis and optimization of structured power/ground networks. IEEE Trans. Comput.-Aid. Des. Integrated Circ. Syst. 1533--1544.
• 34: Teng, C. C., Cheng, Y. K., Rosenbaum, E., and Kang, S. M. 1997. iTEM: A temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 882--893.
• 35: Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual Design Automation Conference, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]
• 36: Ting-Yuan Wang , Charlie Chung-Ping Chen, Thermal-ADI: a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.691-700, August 2003 [doi>10.1109/TVLSI.2003.812372]
• 37: Hao Yu , Chunta Chu , Lei He, Off-chip decoupling capacitor allocation for chip package co-design, Proceedings of the 44th annual Design Automation Conference, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278635]
• 38: Yu, H., He, L., and Tan, S. BMAS-. 2005. Block structure preserving model reduction. In IEEE International Workshop on Behavioral Modeling and Simulation (BMAS).
• 39: Hao Yu , Joanna Ho , Lei He, Simultaneous power and thermal integrity driven via stapling in 3D ICs, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233666]
• 40: Hao Yu , Yiyu Shi , Lei He, Fast analysis of structured power grid by triangularization based structure preserving model order reduction, Proceedings of the 43rd annual Design Automation Conference, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146965]
• 41: Hao Yu , Yiyu Shi , Lei He , Tanay Karnik, Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany [doi>10.1145/1165573.1165611]
• 42: Zhan, Y. and Sapatnekar, S. S. 2007. High efficiency green function-based thermal simulation algorithms. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst.
• 43: Zhao, J., Zhang, J., and Fang, J. 1998. Effects of power/ground via distribution on the power/ground performance of C4/BGA packages. In Proceedings of the Conference on IEEE Electrical Performance of Electronic Packaging (EPEP).
• 44: Zhao, M., Panda, R., and et. al. 2002a. Hierarchical analysis of power distribution networks. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst., 159--168.
• 45: Zhao, S., Roy, K., and Koh, C. 2002b. Decoupling capacitance allocation and its application to power supply noise aware floorplanning. IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 81--92.
• 46: Zheng, H., Krauter, B., and Pileggi, L. 2003. On-Package decoupling optimization with package macromodels. In Proceedings of the IEEE Custom Integrated Circuits Conference.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design

Keywords:
Thermal and power integrity, macromodeling, parametric 3D-IC design