ACM Home Page
Please provide us with feedback. Feedback
Playing the trade-off game: Architecture exploration using Coffeee
Full text PdfPdf (1.11 MB)
Source
ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 14 ,  Issue 3  (May 2009) table of contents
Article No. 36  
Year of Publication: 2009
ISSN:1084-4309
Authors
Praveen Raghavan  IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium
Murali Jayapala  IMEC vzw, Belgium
Andy Lambrechts  IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium
Javed Absar  ST Microelectronics, Bristol, UK
Francky Catthoor  IMEC vzw, Belgium and ESAT, Katholieke Universiteit Leuven, Belgium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 30,   Downloads (12 Months): 123,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1529255.1529258
What is a DOI?

ABSTRACT

Modern mobile devices need to be extremely energy efficient. Due to the growing complexity of these devices, energy-aware design exploration has become increasingly important. Current exploration tools often do not support energy estimation, or require the design to be very detailed before estimation is possible. It is important to get early feedback on both performance and energy consumption during all phases of the design and at higher abstraction levels. This article presents a unified optimization and exploration framework to explore source-level transformation to processor architecture design space. The proposed retargetable compiler and simulator framework can map applications to a range of processors and memory configurations, simulate, and report detailed performance and energy estimates. An accurate and consistent energy modeling approach is introduced which can estimate the energy consumption of processor and memories at a component level, which can help to guide the design process. Fast energy-aware architecture exploration is illustrated by modeling both state-of-the-art processors as well as other architectures. Various design trade-offs are also illustrated on different academic as well as industrial benchmarks from both the wireless communication and multimedia domain. We also illustrate a design space exploration on different applications and show that there is large trade-off space between application performance, energy consumption, and area. We show that the proposed framework is consistent, accurate, and covers a large design space including various novel low-power extensions in a unified framework.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
Ascia, G., Catania, V., Palesi, M., and Patti, D. 2003. Epic-Explorer: A parameterized VLIW-based platform framework for design space exploration. In Proceedings of the ESTIMedia Conference, 3--4.
4
 
5
Baron, M. 2005. Cortex a8: High speed, low power. In Microprocessor Report.
 
6
Benini, L., Bruni, D., Chinosi, M., Silvano, C., and Zaccaria, V. 2002. A power modeling and estimation framework for VLIW-based embedded system. ST J. Syst. Res. 3, 1, 110--118.
 
7
Brockmeyer, E., Ghez, C., Baetens, W., and Catthoor, F. 2000. Unified Low-Power Design Flow for Data-Dominated Multi-Media and Telecom Applications. Kluwer Academic, Boston, MA.
8
 
9
Cadence, Inc. 2006. Cadence SoC Encounter User Guide. Cadence, Inc.
10
11
 
12
CoWare, Inc. 2008. CoWare processor designer. www.coware.com/products/processordesigner.php.
13
 
14
15
 
16
Faraday Technology Corporation. 2007. Faraday UMC 90nm RVT Standard Cell Library. http://www.faraday-tech.com.
 
17
Anup Gangwar , M. Balakrishnan , Anshul Kumar, Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.1, p.1-es, January 2007
 
18
 
19
 
20
 
21
 
22
 
23
 
24
 
25
Lambrechts, A., Raghavan, P., Jayapala, M., Catthoor, F., and Verkest, D. 2007. Energy vs. performance trade-offs and interconnect-aware design for coarse grained reconfigurable processors. In Proceedings of the Asia and South Pacific Design Automation Conference Ph.D. Forum.
26
 
27
LSF. 2002. LSF: Liberty simulation framework 1.0. http://liberty.princeton.edu/Software/LSE.
 
28
Mediabench. Mediabench homepage.http://www.cs.ucla.edu/leec/mediabench.
 
29
Mei, B., Vernalde, S., Verkest, D., Man, H. D., and Lauwereins, R. 2003. ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix. In Proceedings of the Conference on Field-Programmable Logic and Applications.
 
30
 
31
Rabbah, R. M., Bratt, I., Asanovic, K., and Agarwal, A. 2004. Versatility and versabench: A new metric and a benchmark suite for flexible architectures. http://groups.csail.mit.edu/cag/versabench/MIT-LCS-TM-646.pdf.
 
32
 
33
 
34
Rixner, S., Dally, W. J., Khailany, B., Mattson, P. R., Kapasi, U. J., and Owens, J. D. 2000. Register organization for media processing. In Proceedings of the International Symposium on High-Performance Computer Architectures (HPCA'00), 375--386.
 
35
Schneider, M., Blume, H., and Noll, T. G. 2004. Power estimation on functional level for programmable processors. Adv. Radio Sci. 2, 215--219.
 
36
Schuster, T., Bougard, B., Raghavan, P., Priewasser, R., Novo, D., Vanderperre, L., and Catthoor, F. 2007. Design of a low power pre-synchronization ASIP for multimode SDR terminals. In Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS'07).
 
37
38
 
39
Starcore DSP Techology. 2000. SC140 DSP Core Reference Manual. Starcore DSP Techology, http://www.starcore-dsp.com.
 
40
SUIF. 2001. SUIF2 compiler system. http://suif.stanford.edu.
 
41
Synfora, Inc. 2008. PICO express. http://www.synfora.com.
 
42
Synopsys, Inc. 2006a. Design Compiler User Guide. Synopsys, Inc.
 
43
Synopsys, Inc. 2006b. Prime Power User Guide. Synopsys, Inc.
 
44
Target. 2008. IP designer. http://www.retarget.com.
 
45
Texas Instruments, Inc. 2006. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. http://www.ti.com/.
 
46
 
47
Trimaran. 1999. Trimaran 2.0: An infrastructure for research in instruction-level parallelism. http://www.trimaran.org.
 
48
Wiegand, T., Sullivan, G. J., Bjontegaard, G., and Luthra, A. 2003. Overview of the H.264/AVC video coding standard. IEEE Trans. Circ. Syst. Video Technol. 13, 7, 560--576.
49

Collaborative Colleagues:
Praveen Raghavan: colleagues
Murali Jayapala: colleagues
Andy Lambrechts: colleagues
Javed Absar: colleagues
Francky Catthoor: colleagues